diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2019-11-01 16:58:10 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-04 11:33:32 +0000 |
| commit | 3d4f51ef695ff2473b963a33cfdfeb4d864d3f4a (patch) | |
| tree | 07bda561796e7a952c5b97cec116c6f9642a7794 /src | |
| parent | 1845fc89476df67c5981cb2d67ddb11d271154bb (diff) | |
| download | coreboot-3d4f51ef695ff2473b963a33cfdfeb4d864d3f4a.tar.xz | |
mb/google/drallion: Correct GPP_E7 as stop pin
Current design reset pin is connected to PLTRST.
GPP_E7 is stop pin for touch. Reserve reset pin for
next stage implement.
BUG=b:143733039
BRANCH=N/A
TEST=check touch screen can work properly
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3ebd56ab49b87da425583da04f082e69293a023e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/drallion/variants/drallion/devicetree.cb | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 0de2e94e4b..ed44f4fec1 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -322,8 +322,8 @@ chip soc/intel/cannonlake register "generic.desc" = ""Wacom Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" - register "generic.reset_delay_ms" = "20" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "generic.stop_delay_ms" = "20" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" register "generic.enable_delay_ms" = "55" register "generic.has_power_resource" = "1" @@ -338,9 +338,9 @@ chip soc/intel/cannonlake register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" - register "generic.reset_gpio" = + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" - register "generic.reset_delay_ms" = "10" + register "generic.stop_delay_ms" = "10" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" register "generic.enable_delay_ms" = "55" @@ -355,8 +355,8 @@ chip soc/intel/cannonlake register "desc" = ""Melfas Touchscreen"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "probed" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" - register "reset_delay_ms" = "10" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "stop_delay_ms" = "10" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" register "enable_delay_ms" = "55" register "has_power_resource" = "1" |