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authorElyes HAOUAS <ehaouas@noos.fr>2019-12-11 08:07:55 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-12-12 15:11:22 +0000
commit442fb05acf149a178848931dfe123263e1748c90 (patch)
treecfe471432aac1e6d67188e3f724d3480c39e1250 /src
parent2cd02610ee35eedc63a27c3fd1460258c273329a (diff)
downloadcoreboot-442fb05acf149a178848931dfe123263e1748c90.tar.xz
nb/{haswell,i945,sandybridge}: Drop outdated comment
'e7525/northbridge.c' does not exist anymore. Change-Id: I5520760f59a3c6f89afb1360b12bd9763fba562a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37653 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Mimoja <coreboot@mimoja.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/haswell/northbridge.c1
-rw-r--r--src/northbridge/intel/i945/northbridge.c1
-rw-r--r--src/northbridge/intel/sandybridge/northbridge.c1
3 files changed, 0 insertions, 3 deletions
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index c047c39ea7..1efa6603d2 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -92,7 +92,6 @@ static const char *northbridge_acpi_name(const struct device *dev)
/* TODO We could determine how many PCIe busses we need in
* the bar. For now that number is hardcoded to a max of 64.
- * See e7525/northbridge.c for an example.
*/
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index dde1b110f4..bcecd8854b 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -165,7 +165,6 @@ void northbridge_write_smram(u8 smram)
/* TODO We could determine how many PCIe busses we need in
* the bar. For now that number is hardcoded to a max of 64.
- * See e7525/northbridge.c for an example.
*/
static struct device_operations pci_domain_ops = {
.read_resources = mch_domain_read_resources,
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 6337d69020..b34f07d696 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -258,7 +258,6 @@ static const char *northbridge_acpi_name(const struct device *dev)
/* TODO We could determine how many PCIe busses we need in
* the bar. For now that number is hardcoded to a max of 64.
- * See e7525/northbridge.c for an example.
*/
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,