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authorGreg Watson <jarrah@users.sourceforge.net>2004-01-22 00:02:12 +0000
committerGreg Watson <jarrah@users.sourceforge.net>2004-01-22 00:02:12 +0000
commit47624a8e1356fa0f60641bc71f9e096db133820f (patch)
tree0d0bce0687465c9da75e2b5bcd4e573f936cdc79 /src
parent6cc2a5c4c420c7a520e5c173bb57bce2d817e665 (diff)
downloadcoreboot-47624a8e1356fa0f60641bc71f9e096db133820f.tar.xz
*** empty log message ***
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/motorola/sandpoint/init.c11
1 files changed, 9 insertions, 2 deletions
diff --git a/src/mainboard/motorola/sandpoint/init.c b/src/mainboard/motorola/sandpoint/init.c
index 9496b7a94c..de50a91be5 100644
--- a/src/mainboard/motorola/sandpoint/init.c
+++ b/src/mainboard/motorola/sandpoint/init.c
@@ -44,6 +44,8 @@ void pnp_output(char address, char data)
void
board_init(void)
{
+ unsigned char reg8;
+
/*
* Configure FLASH
*/
@@ -54,11 +56,16 @@ board_init(void)
/*
* Enable UART0
+ *
+ * NOTE: this configuration assumes that the PCI/ISA IO
+ * address space is properly configured by default on board
+ * reset. While this seems to be the case with the X3, it may not
+ * always work.
*/
pnp_output(0x07, 6); /* LD 6 = UART0 */
pnp_output(0x30, 0); /* Dectivate */
- pnp_output(0x60, UART0_IO_BASE >> 8); /* IO Base */
- pnp_output(0x61, UART0_IO_BASE & 0xFF); /* IO Base */
+ pnp_output(0x60, TTYS0_BASE >> 8); /* IO Base */
+ pnp_output(0x61, TTYS0_BASE & 0xFF); /* IO Base */
pnp_output(0x30, 1); /* Activate */
uart8250_init(TTYS0_BASE, 115200/TTYS0_BAUD, TTYS0_LCS);
printk_info("Board initialized...\n");