summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorPatrick Georgi <pgeorgi@chromium.org>2015-07-06 20:50:33 +0200
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-07-07 02:35:52 +0200
commit49a8c8a3adc94c76542389b0bb3dcabec9eb7280 (patch)
treef66b691ab61398226e8ae5581c6dcd2563b0624a /src
parent11ac97bb2b4f9d58e899880f536d437a305f3829 (diff)
downloadcoreboot-49a8c8a3adc94c76542389b0bb3dcabec9eb7280.tar.xz
sandybridge: provide monotonic timer function
This fixes building the ELOG_GSMI feature by using the TSC as time source for the flash drivers. It's not the most precise clock, but should be good enough for the purpose. Change-Id: I2d416c34268236228300a9e868628c35e22bf40c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10813 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/sandybridge/udelay.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c
index b150253247..7c9838015a 100644
--- a/src/northbridge/intel/sandybridge/udelay.c
+++ b/src/northbridge/intel/sandybridge/udelay.c
@@ -53,3 +53,23 @@ void udelay(u32 us)
} while ((tsc.hi < tsc1.hi)
|| ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
}
+
+#if CONFIG_LAPIC_MONOTONIC_TIMER && !defined(__PRE_RAM__)
+#include <timer.h>
+
+void timer_monotonic_get(struct mono_time *mt)
+{
+ tsc_t tsc;
+ msr_t msr;
+ u32 fsb = 100, divisor;
+ u32 d; /* ticks per us */
+
+ msr = rdmsr(0xce);
+ divisor = (msr.lo >> 8) & 0xff;
+ d = fsb * divisor; /* On Core/Core2 this is divided by 4 */
+
+ tsc = rdtsc();
+
+ mt->microseconds = (long)((((uint64_t)tsc.hi << 32) | tsc.lo) / d);
+}
+#endif