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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2016-04-09 21:47:18 -0500
committerMartin Roth <martinroth@google.com>2016-04-11 17:29:58 +0200
commit54e055179dd19307a8e8ac2c94b224ebe988ed5d (patch)
tree6190df9865ccae40b4fe6340587a733edf2b0daf /src
parent2c34e3155c37a5bb2cca28334ca35eac98544c22 (diff)
downloadcoreboot-54e055179dd19307a8e8ac2c94b224ebe988ed5d.tar.xz
nb/amd/amdfam10: Write MCT variables to flash after PCI configuration
The SPI controller needs to be set up on devices such as the SP5100 before it can be accessed to write MCT backup data. Move the backup data write after PCI configuration has been completed. Change-Id: Ibcf31755242ac058407a422ce8aa33d6b0b293c7 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14305 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/amd/amdfam10/northbridge.c11
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/s3utils.c8
2 files changed, 7 insertions, 12 deletions
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 06079dd98b..da93175b21 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -1975,10 +1975,6 @@ static void root_complex_enable_dev(struct device *dev)
/* Do not delay UMA setup, as a device on the PCI bus may evaluate
the global uma_memory variables already in its enable function. */
if (!done) {
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && IS_ENABLED(CONFIG_DIMM_DDR3)
- save_mct_information_to_nvram();
-#endif
-
setup_bsp_ramtop();
setup_uma_memory();
done = 1;
@@ -1992,7 +1988,14 @@ static void root_complex_enable_dev(struct device *dev)
}
}
+static void root_complex_finalize(void *chip_info) {
+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && IS_ENABLED(CONFIG_DIMM_DDR3)
+ save_mct_information_to_nvram();
+#endif
+}
+
struct chip_operations northbridge_amd_amdfam10_root_complex_ops = {
CHIP_NAME("AMD Family 10h/15h Root Complex")
.enable_dev = root_complex_enable_dev,
+ .final = root_complex_finalize,
};
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
index fe7707591e..6589a39943 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
@@ -1132,11 +1132,6 @@ int8_t save_mct_information_to_nvram(void)
s3nv_offset &= ~(CONFIG_S3_DATA_SIZE-1);
s3nv_offset += CONFIG_S3_DATA_SIZE;
- /* Set temporary SPI MMIO address */
- device_t lpc_dev = dev_find_slot(0, PCI_DEVFN(0x14, 3));
- uint32_t spi_mmio_prev = pci_read_config32(lpc_dev, 0xa0);
- pci_write_config32(lpc_dev, 0xa0, (spi_mmio_prev & 0x1f) | 0xf0000000);
-
/* Initialize SPI and detect devices */
spi_init();
flash = spi_flash_probe(0, 0);
@@ -1160,9 +1155,6 @@ int8_t save_mct_information_to_nvram(void)
flash->spi->rw = SPI_WRITE_FLAG;
spi_release_bus(flash->spi);
- /* Restore SPI MMIO address */
- pci_write_config32(lpc_dev, 0xa0, spi_mmio_prev);
-
/* Allow training bypass if DIMM configuration is unchanged on next boot */
nvram = 1;
set_option("allow_spd_nvram_cache_restore", &nvram);