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authorSebastian Andrzej Siewior <bigeasy@linutronix.de>2012-10-26 19:01:45 +0200
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-10-26 21:55:17 +0200
commit59e3e0299112070e51c4dabc8f616344e291956f (patch)
tree2a95bed4cde51ccf777b50661ed32c3328ea7a3d /src
parent50dd47bb58bee2ed159c1c5f6eb51dd583094f26 (diff)
downloadcoreboot-59e3e0299112070e51c4dabc8f616344e291956f.tar.xz
northbridge/sch: read the size of main memory from the proper register
I don't know if the size main memory supposed to be in PCI(0,0) reg 0x9c but it is not written there. The size of memory is written in src/northbridge/intel/sch/raminit.c to SCH port(2, 8, 4) (look for "Setting up TOM"). Change-Id: Iea04a5185bda56f61d1c382533d5a0dac429ebbd Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Reviewed-on: http://review.coreboot.org/1629 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/sch/northbridge.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c
index 4ca1248a0b..4c41d68fbd 100644
--- a/src/northbridge/intel/sch/northbridge.c
+++ b/src/northbridge/intel/sch/northbridge.c
@@ -111,10 +111,10 @@ static void pci_domain_set_resources(device_t dev)
printk(BIOS_SPEW, "Base of stolen memory: 0x%08x\n",
pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c));
- tolud = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9c);
- printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08llx\n", tolud << 24);
+ tolud = sch_port_access_read(2, 8, 4);
+ printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08llx\n", tolud);
- tomk = tolud << 14;
+ tomk = tolud / 1024;
tomk_stolen = tomk;
/* Note: subtract IGD device and TSEG. */