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authorMarc Jones <marcj303@gmail.com>2011-07-12 23:02:03 -0600
committerPeter Stuge <peter@stuge.se>2011-07-14 00:43:02 +0200
commit5a91692466d501bde8fab5f9b0dee0a83444ee51 (patch)
treee09e3757537c7265ba43870ed67e49011cde4a11 /src
parent2a561a18deeed436b27cb99cba4b15a4351435a1 (diff)
downloadcoreboot-5a91692466d501bde8fab5f9b0dee0a83444ee51.tar.xz
Set SB800 ROM decode size based on kconfig.
Change-Id: I46ea26b5534064fe1c7e2ce2b2f12cacf18a4d4d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/94 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
Diffstat (limited to 'src')
-rw-r--r--src/southbridge/amd/cimx/sb800/bootblock.c5
-rw-r--r--src/southbridge/amd/sb800/bootblock.c2
2 files changed, 3 insertions, 4 deletions
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
index aaec03cbea..170276ac69 100644
--- a/src/southbridge/amd/cimx/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx/sb800/bootblock.c
@@ -49,10 +49,9 @@ static void enable_rom(void)
dword |= (1 << 0) | (1 << 1) | (1 << 4) | (1 << 6) | (1 << 21);
pci_io_write_config32(dev, 0x48, dword);
- /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */
- /* Set the 4MB enable bits */
+ /* Enable rom access */
word = pci_io_read_config16(dev, 0x6c);
- word = 0xFFC0;
+ word = 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6);
pci_io_write_config16(dev, 0x6c, word);
}
diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c
index 82d80f08a8..18eae24312 100644
--- a/src/southbridge/amd/sb800/bootblock.c
+++ b/src/southbridge/amd/sb800/bootblock.c
@@ -57,7 +57,7 @@ static void sb800_enable_rom(void)
* 0xffe0(0000): 2MB
* 0xffc0(0000): 4MB
*/
- pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */
+ pci_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
/* Enable LPC ROM range end at 0xffff(ffff). */
pci_write_config16(dev, 0x6e, 0xffff);
}