diff options
| author | Felix Held <felix.held@amd.corp-partner.google.com> | 2020-05-15 18:12:35 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-18 07:30:59 +0000 |
| commit | 68975b15cf51902d8dbd5b868b23011c9ee58ac9 (patch) | |
| tree | 00116db27d37e2eafadfc558ad7e65e28556a73d /src | |
| parent | 979e80dc47d4f6bd1c1333c79ef59706d6c9403b (diff) | |
| download | coreboot-68975b15cf51902d8dbd5b868b23011c9ee58ac9.tar.xz | |
soc/amd/picasso: only link soc_util in ramstage
No code that was or will be upstreamed uses functionality from soc_util
in romstage, so only compile and link it for ramstage.
This also allows to fix the SoC type detection in a follow-up patch
using information that FPS-M will be providing in a HOB.
BUG=b:153779573
Change-Id: If96e53608eadd562f6de5a0c370b89e84e43d049
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/picasso/Makefile.inc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index e015fbe057..a82a227c15 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -29,7 +29,6 @@ romstage-$(CONFIG_PICASSO_UART) += uart.c romstage-y += tsc_freq.c romstage-y += southbridge.c romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c -romstage-y += soc_util.c romstage-y += psp.c romstage-y += mtrr.c romstage-y += config.c |