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authorFurquan Shaikh <furquan@google.com>2020-07-14 16:08:20 -0700
committerAaron Durbin <adurbin@chromium.org>2020-07-16 16:39:25 +0000
commit6a5c77cc846384dbc10c3546f70245025787ef08 (patch)
tree2898283aef329af50f0c1938bc590b6fa1aee1cb /src
parentddfec569d1c98afd5e038be7614bc0d0a926d2e0 (diff)
downloadcoreboot-6a5c77cc846384dbc10c3546f70245025787ef08.tar.xz
mb/google/zork: Drop redundant romstage GPIO table
Now that the power and reset GPIO configuration for non-PCIe devices is dropped from romstage GPIO table, the tables for pre-v3 and v3 version of schematics are exactly same. So, this change drops the duplicate table and also removes the check for v3 schematics when configuring the pads in romstage. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I67ca9f587c3f47912393ebaf38badcc9d76cc393 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c26
-rw-r--r--src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c24
2 files changed, 6 insertions, 44 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
index e8dafee059..135eccaa54 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
@@ -9,22 +9,7 @@
#include <boardid.h>
#include <variant/gpio.h>
-static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = {
- /* PCIE_RST1_L - Variable timings (May remove) */
- PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
- /* NVME_AUX_RESET_L */
- PAD_GPO(GPIO_40, HIGH),
- /* CLK_REQ0_L - WIFI */
- PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP),
- /* CLK_REQ1_L - SD Card */
- PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP),
- /* CLK_REQ2_L - NVMe */
- PAD_NF(GPIO_116, CLK_REQ2_L, PULL_UP),
- /* SD_AUX_RESET_L */
- PAD_GPO(GPIO_142, HIGH),
-};
-
-static const struct soc_amd_gpio gpio_set_stage_rom_v3[] = {
+static const struct soc_amd_gpio gpio_set_stage_rom[] = {
/* PCIE_RST1_L - Variable timings (May remove) */
PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
/* NVME_AUX_RESET_L */
@@ -157,13 +142,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
const __weak
struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size)
{
- if (variant_uses_v3_schematics()) {
- *size = ARRAY_SIZE(gpio_set_stage_rom_v3);
- return gpio_set_stage_rom_v3;
- }
-
- *size = ARRAY_SIZE(gpio_set_stage_rom_pre_v3);
- return gpio_set_stage_rom_pre_v3;
+ *size = ARRAY_SIZE(gpio_set_stage_rom);
+ return gpio_set_stage_rom;
}
const __weak
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
index 106ebd629f..b3cbf67307 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
@@ -9,20 +9,7 @@
#include <boardid.h>
#include <variant/gpio.h>
-static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = {
- /* NVME_AUX_RESET_L */
- PAD_GPO(GPIO_40, HIGH),
- /* CLK_REQ0_L - WIFI */
- PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP),
- /* CLK_REQ1_L - SD Card */
- PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP),
- /* CLK_REQ4_L - SSD */
- PAD_NF(GPIO_132, CLK_REQ4_L, PULL_UP),
- /* SD_AUX_RESET_L */
- PAD_GPO(GPIO_142, HIGH),
-};
-
-static const struct soc_amd_gpio gpio_set_stage_rom_v3[] = {
+static const struct soc_amd_gpio gpio_set_stage_rom[] = {
/* NVME_AUX_RESET_L */
PAD_GPO(GPIO_40, HIGH),
/* CLK_REQ0_L - WIFI */
@@ -151,13 +138,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
const __weak
struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size)
{
- if (variant_uses_v3_schematics()) {
- *size = ARRAY_SIZE(gpio_set_stage_rom_v3);
- return gpio_set_stage_rom_v3;
- }
-
- *size = ARRAY_SIZE(gpio_set_stage_rom_pre_v3);
- return gpio_set_stage_rom_pre_v3;
+ *size = ARRAY_SIZE(gpio_set_stage_rom);
+ return gpio_set_stage_rom;
}
const __weak