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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2015-10-29 04:15:10 -0500
committerRonald G. Minnich <rminnich@gmail.com>2015-10-30 16:33:46 +0100
commit6b171b3163eb3a4e8bcfd53f0d2d8b47d619b78d (patch)
tree9e33e54b53313f09fc1b8016650eaea87fd3788b /src
parente67d2404444c473f1fbec849f5175c13a4e3743f (diff)
downloadcoreboot-6b171b3163eb3a4e8bcfd53f0d2d8b47d619b78d.tar.xz
cpu/amd/model_fxx: Backport APIC code and debug aids from Family 10h
Backport a handful of debugging routines and the extended APIC initialization code from Family 10h support to K8 support. Change-Id: I08cc5c8bc65635ce09a69e32940dd7edd8d3be87 TEST: Booted ASUS KFSN4-DRE with 1x Opteron 8222 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12251 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/cpu/amd/model_fxx/init_cpus.c29
-rw-r--r--src/cpu/amd/model_fxx/model_fxx_init.c1
2 files changed, 25 insertions, 5 deletions
diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c
index 12d3a95962..f30ff0a03e 100644
--- a/src/cpu/amd/model_fxx/init_cpus.c
+++ b/src/cpu/amd/model_fxx/init_cpus.c
@@ -188,6 +188,15 @@ void allow_all_aps_stop(u32 bsp_apicid)
lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 0x44);
}
+static void enable_apic_ext_id(u32 node)
+{
+ u32 val;
+
+ val = pci_read_config32(NODE_HT(node), 0x68);
+ val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
+ pci_write_config32(NODE_HT(node), 0x68, val);
+}
+
static void STOP_CAR_AND_CPU(void)
{
disable_cache_as_ram(); // inline
@@ -205,6 +214,19 @@ static u32 init_cpus(u32 cpu_init_detectedx)
u32 apicid;
struct node_core_id id;
+#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)
+ /* Please refer to the calculations and explaination in cache_as_ram.inc before modifying these values */
+ uint32_t max_ap_stack_region_size = CONFIG_MAX_CPUS * CONFIG_DCACHE_AP_STACK_SIZE;
+ uint32_t max_bsp_stack_region_size = CONFIG_DCACHE_BSP_STACK_SIZE + CONFIG_DCACHE_BSP_STACK_SLUSH;
+ uint32_t bsp_stack_region_upper_boundary = CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE;
+ uint32_t bsp_stack_region_lower_boundary = bsp_stack_region_upper_boundary - max_bsp_stack_region_size;
+ void * lower_stack_region_boundary = (void*)(bsp_stack_region_lower_boundary - max_ap_stack_region_size);
+ if (((void*)(sysinfo + 1)) > lower_stack_region_boundary)
+ printk(BIOS_WARNING,
+ "sysinfo extends into stack region (sysinfo range: [%p,%p] lower stack region boundary: %p)\n",
+ sysinfo, sysinfo + 1, lower_stack_region_boundary);
+#endif
+
/*
* already set early mtrr in cache_as_ram.inc
*/
@@ -217,9 +239,8 @@ static u32 init_cpus(u32 cpu_init_detectedx)
core0 is done at first --- use wait_all_core0_started */
if (id.coreid == 0) {
set_apicid_cpuid_lo(); /* only set it on core0 */
-#if CONFIG_ENABLE_APIC_EXT_ID
- enable_apic_ext_id(id.nodeid);
-#endif
+ if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID))
+ enable_apic_ext_id(id.nodeid);
}
enable_lapic();
@@ -249,7 +270,6 @@ static u32 init_cpus(u32 cpu_init_detectedx)
/* get the apicid, it may be lifted already */
apicid = lapicid();
-#if 0
// show our apicid, nodeid, and coreid
if (id.coreid == 0) {
if (id.nodeid != 0) //all core0 except bsp
@@ -257,7 +277,6 @@ static u32 init_cpus(u32 cpu_init_detectedx)
} else { //all other cores
print_apicid_nodeid_coreid(apicid, id, " corex: ");
}
-#endif
if (cpu_init_detectedx) {
print_apicid_nodeid_coreid(apicid, id,
diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index 268f1b2dad..db936f8933 100644
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -504,6 +504,7 @@ static void model_fxx_init(device_t dev)
msr.hi |= 1 << (33 - 32);
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
+ printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
#endif
id = get_node_core_id(read_nb_cfg_54()); // pre e0 nb_cfg_54 can not be set