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authorShaunak Saha <shaunak.saha@intel.com>2017-12-13 09:37:05 -0800
committerAaron Durbin <adurbin@chromium.org>2018-01-16 19:31:39 +0000
commit7210ec0dcaca84957a5ebe9ea6e222d55a1431bb (patch)
tree3ee30a36f71a825bc49e1fb4f7fef695d9a67fc3 /src
parent0a19b080ef03ba50d111bd966c45ca90cf1507d6 (diff)
downloadcoreboot-7210ec0dcaca84957a5ebe9ea6e222d55a1431bb.tar.xz
soc/intel/apollolake: Set ACPI_FADT_LOW_PWR_IDLE_S0 for S0ix
This patch sets the ACPI FADT flag ACPI_FADT_LOW_PWR_IDLE_S0 if S0IX is enabled for the platform. TEST= Boot to OS and check the ACPI_FADT_LOW_PWR_IDLE_S0 flag is set in FACP table. Change-Id: Ibb43d5c8024dcdf753416e4bd2a457991cc7a433 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/23095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/apollolake/acpi.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index 1449a36619..5e42091965 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -153,6 +153,9 @@ int soc_madt_sci_irq_polarity(int sci)
void soc_fill_fadt(acpi_fadt_t *fadt)
{
+ const struct soc_intel_apollolake_config *cfg;
+ struct device *dev = SA_DEV_ROOT;
+
fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR;
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
@@ -166,6 +169,15 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
fadt->x_pm_tmr_blk.addrl = ACPI_BASE_ADDRESS + PM1_TMR;
+
+ if (!dev || !dev->chip_info) {
+ printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
+ return;
+ }
+ cfg = dev->chip_info;
+
+ if(cfg->lpss_s0ix_enable)
+ fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
}
void soc_power_states_generation(int core_id, int cores_per_package)