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authorElia Yehuda <z4ziggy@gmail.com>2009-07-05 15:50:30 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2009-07-05 15:50:30 +0000
commit76a88d0805a42f3759f1444ab62760f5160fc999 (patch)
tree4b49ccbee6f032a5c069e01a2a747aefcd0b3903 /src
parentbd4f2f808c258bc58814f3a230d0788a0b0fbd26 (diff)
downloadcoreboot-76a88d0805a42f3759f1444ab62760f5160fc999.tar.xz
Various Intel 82810/82810E changes which allow onboard VGA to work.
At the same time also make the 82810 code handle 82810E. - Set SMRAM register according to CONFIG_VIDEO_MB value: - 512 means 512 KB - 1 means 1 MB - Every other value for CONFIG_VIDEO_MB (e.g. 0) disables VGA. This is not very clean, changing CONFIG_VIDEO_MB to CONFIG_VIDEO_KB in a future patch may be nicer. - Set MISSC2 register bits as required per datasheet to make VGA work. The code handles both 82810 and 82810E. - northbridge.c: Add __pci_driver entry for the Intel 82810E. Also: - Rename PAM register #define to PAMR as per datasheet. - Drop unused/commented code for now. - Don't explicitly set GMCHCFG for now, the default works ok. We'll have to figure out the proper/ideal settings later. The code is based on a patch from Elia Yehuda <z4ziggy@gmail.com> but has been modified quite a bit for correctness and minimalism. Tested on hardware with a slightly modified MS-6178 target, patches to enable onboard-VGA for MS-6178 will follow. Signed-off-by: Elia Yehuda <z4ziggy@gmail.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4398 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/i82810/i82810.h2
-rw-r--r--src/northbridge/intel/i82810/northbridge.c23
-rw-r--r--src/northbridge/intel/i82810/raminit.c66
3 files changed, 50 insertions, 41 deletions
diff --git a/src/northbridge/intel/i82810/i82810.h b/src/northbridge/intel/i82810/i82810.h
index 94993ec540..554302924c 100644
--- a/src/northbridge/intel/i82810/i82810.h
+++ b/src/northbridge/intel/i82810/i82810.h
@@ -35,7 +35,7 @@
*/
#define GMCHCFG 0x50 /* GMCH Configuration */
-#define PAM 0x51 /* Programmable Attributes */
+#define PAMR 0x51 /* Programmable Attributes */
#define DRP 0x52 /* DRAM Row Population */
#define DRAMT 0x53 /* DRAM Timing */
#define FDHC 0x58 /* Fixed DRAM Hole Control */
diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c
index c705b55a45..22ea99ef7c 100644
--- a/src/northbridge/intel/i82810/northbridge.c
+++ b/src/northbridge/intel/i82810/northbridge.c
@@ -46,12 +46,20 @@ static struct device_operations northbridge_operations = {
.ops_pci = 0,
};
-static const struct pci_driver northbridge_driver __pci_driver = {
+/* Intel 82810/82810-DC100 */
+static const struct pci_driver i810_northbridge_driver __pci_driver = {
.ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x7120,
};
+/* Intel 82810E */
+static const struct pci_driver i810e_northbridge_driver __pci_driver = {
+ .ops = &northbridge_operations,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = 0x7124,
+};
+
static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek)
{
@@ -139,6 +147,19 @@ static void pci_domain_set_resources(device_t dev)
/* Convert tomk from MB to KB. */
tomk = tomk << 10;
+#ifdef CONFIG_VIDEO_MB
+ /* Check for VGA reserved memory. */
+ if (CONFIG_VIDEO_MB == 512) {
+ tomk -= 512;
+ printk_debug("Allocating %s RAM for VGA\n", "512KB");
+ } else if (CONFIG_VIDEO_MB == 1) {
+ tomk -= 1024 ;
+ printk_debug("Allocating %s RAM for VGA\n", "1MB");
+ } else {
+ printk_debug("Allocating %s RAM for VGA\n", "0MB");
+ }
+#endif
+
/* Compute the top of Low memory. */
tolmk = pci_tolm >> 10;
if (tolmk >= tomk) {
diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c
index d5b4864104..c9561eb779 100644
--- a/src/northbridge/intel/i82810/raminit.c
+++ b/src/northbridge/intel/i82810/raminit.c
@@ -1,9 +1,9 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2008 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2007-2009 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
- * Copyright (C) 2008 Elia Yehuda <z4ziggy@gmail.com>
+ * Copyright (C) 2008-2009 Elia Yehuda <z4ziggy@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -360,45 +360,33 @@ Public interface.
static void sdram_set_registers(void)
{
- unsigned long val;
-
- /* TODO */
- pci_write_config8(PCI_DEV(0, 0, 0), GMCHCFG, 0x60);
-
- /* PAMR: Programmable Attributes Register
- * Every pair of bits controls an address range:
- * 00 = Disabled, all accesses are forwarded to the ICH
- * 01 = Read Only
- * 10 = Write Only
- * 11 = Read/Write
-
- * Bit Range
- * 7:6 000F0000 - 000FFFFF
- * 5:4 000E0000 - 000EFFFF
- * 3:2 000D0000 - 000DFFFF
- * 1:0 000C0000 - 000CFFFF
- */
+ u8 reg8;
+ u16 reg16, did;
- /* Ideally, this should be R/W for as many ranges as possible. */
- pci_write_config8(PCI_DEV(0, 0, 0), PAM, 0xff);
+ did = pci_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
- /* Enabling the VGA Framebuffer currently screws up the rest of the boot.
- * Disable for now */
+ /* Ideally, this should be R/W for as many ranges as possible. */
+ pci_write_config8(PCI_DEV(0, 0, 0), PAMR, 0xff);
- /* Enable 1MB framebuffer. */
- //pci_write_config8(PCI_DEV(0, 0, 0), SMRAM, 0xC0);
-
- //val = pci_read_config16(PCI_DEV(0, 0, 0), MISSC);
- /* Preserve reserved bits. */
- //val &= 0xff06;
- /* Set graphics cache window to 32MB, no power throttling. */
- //val |= 0x0001;
- //pci_write_config16(PCI_DEV(0, 0, 0), MISSC, val);
-
- //val = pci_read_config8(PCI_DEV(0, 0, 0), MISSC2);
- /* Enable graphics palettes and clock gating (not optional!) */
- //val |= 0x06;
- //pci_write_config8(PCI_DEV(0, 0, 0), MISSC2, val);
+ /* Set size for onboard-VGA framebuffer. */
+ reg8 = pci_read_config8(PCI_DEV(0, 0, 0), SMRAM);
+ reg8 &= 0x3f; /* Disable graphics (for now). */
+ if (CONFIG_VIDEO_MB == 512)
+ reg8 |= (1 << 7); /* Enable graphics (512KB RAM). */
+ else if (CONFIG_VIDEO_MB == 1)
+ reg8 |= (1 << 7) | (1 << 6); /* Enable graphics (1MB RAM). */
+ pci_write_config8(PCI_DEV(0, 0, 0), SMRAM, reg8);
+
+ /* MISSC2: Bits 1, 2, 6, 7 must be set for VGA (see datasheet). */
+ reg8 = pci_read_config8(PCI_DEV(0, 0, 0), MISSC2);
+ reg8 |= (1 << 1); /* Instruction Parser Unit-Level Clock Gating */
+ reg8 |= (1 << 2); /* Palette Load Select */
+ if (did == 0x7124) {
+ /* Bits 6 and 7 are only available on 82810E (not 82810). */
+ reg8 |= (1 << 6); /* Text Immediate Blit */
+ reg8 |= (1 << 7); /* Must be 1 as per datasheet. */
+ }
+ pci_write_config8(PCI_DEV(0, 0, 0), MISSC2, reg8);
}
static void sdram_set_spd_registers(void)
@@ -437,7 +425,7 @@ static void sdram_enable(void)
do_ram_command(RAM_COMMAND_MRS);
udelay(2);
- /* 5. Normal operation (enables refresh) */
+ /* 5. Normal operation (enables refresh at 15.6usec). */
PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
do_ram_command(RAM_COMMAND_NORMAL);
udelay(1);