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authorFelix Singer <felixsinger@posteo.net>2020-09-04 10:23:50 +0000
committerMichael Niewöhner <c0d3z3r0@review.coreboot.org>2020-09-07 21:35:29 +0000
commit7e396f380eb480aac7546bc65c16e4585f7dfc78 (patch)
treedb73b3a0d1fe4e16b0dea1809c3d4ea6ae8774bc /src
parentbe50ab0878ac61eca145087d5969fbefed4ff3ba (diff)
downloadcoreboot-7e396f380eb480aac7546bc65c16e4585f7dfc78.tar.xz
mb/system76/lemp9: Add SMBIOS descriptions to root ports
Change-Id: Ie663d424edbbeeb8f5691b00f3977f7501e9ab45 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/system76/lemp9/devicetree.cb9
1 files changed, 6 insertions, 3 deletions
diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb
index 0cbd5d2d29..31f411d085 100644
--- a/src/mainboard/system76/lemp9/devicetree.cb
+++ b/src/mainboard/system76/lemp9/devicetree.cb
@@ -175,7 +175,7 @@ chip soc/intel/cannonlake
end
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 on # PCI Express Port 8
- device pci 00.0 on end # x1 M.2/E 2230 (WLAN)
+ device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1)
register "PcieRpEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "1"
register "PcieClkSrcUsage[2]" = "7"
@@ -184,25 +184,28 @@ chip soc/intel/cannonlake
chip drivers/intel/wifi
device pci 00.0 on end
end
+ smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
end
device pci 1d.0 on # PCI Express Port 9
- device pci 00.0 on end # x4 M.2/M 2280 (Slot 2)
+ device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2)
register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[4]" = "8"
register "PcieClkSrcClkReq[4]" = "4"
register "PcieRpSlotImplemented[8]" = "1"
+ smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
end
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 on # PCI Express Port 13
- device pci 00.0 on end # x4 M.2/M 2280 (Slot 1)
+ device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1)
register "PcieRpEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "1"
register "PcieClkSrcUsage[5]" = "12"
register "PcieClkSrcClkReq[5]" = "5"
register "PcieRpSlotImplemented[12]" = "1"
+ smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
end
device pci 1d.5 off end # PCI Express Port 14
device pci 1d.6 off end # PCI Express Port 15