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authorNils Jacobs <njacobs8@hetnet.nl>2010-12-30 19:23:29 +0000
committerStefan Reinauer <stepan@openbios.org>2010-12-30 19:23:29 +0000
commit8098e429445723a60cf7772777385259e2c498bb (patch)
tree616064ee9a2e2ef9ac9a83dd3b03f5220baae484 /src
parent8cf54c9f236afef6b74b6510983bd25e8536055a (diff)
downloadcoreboot-8098e429445723a60cf7772777385259e2c498bb.tar.xz
Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge code
and fix CIS mode comments. Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6225 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/cpu/amd/model_gx2/cpureginit.c9
-rw-r--r--src/southbridge/amd/cs5535/early_setup.c6
-rw-r--r--src/southbridge/amd/cs5536/early_setup.c2
3 files changed, 5 insertions, 12 deletions
diff --git a/src/cpu/amd/model_gx2/cpureginit.c b/src/cpu/amd/model_gx2/cpureginit.c
index cfb86aa327..0fc852d531 100644
--- a/src/cpu/amd/model_gx2/cpureginit.c
+++ b/src/cpu/amd/model_gx2/cpureginit.c
@@ -88,16 +88,13 @@ void cpuRegInit (void)
msr.lo = 0x00000603C;
wrmsr(msrnum, msr);
-/* Only do this if we are building for 5535 */
/* FooGlue Setup */
-#if 1
- /* Enable CIS mode B in FooGlue */
- msrnum = MSR_FG + 0x10;
+ /* Set CS5535/CS5536 mode in FooGlue */
+ msrnum = FG_GIO_MSR_SEL;
msr = rdmsr(msrnum);
msr.lo &= ~3;
- msr.lo |= 2; /* ModeB */
+ msr.lo |= 2; /* IIOC mode CS5535/CS5536 enable. (according to Jordan Crouse the databook is wrong bits 1:0 have to be 2 instead of 1) */
wrmsr(msrnum, msr);
-#endif
/* Disable DOT PLL. Graphics init will enable it if needed. */
msrnum = GLCP_DOTPLL;
diff --git a/src/southbridge/amd/cs5535/early_setup.c b/src/southbridge/amd/cs5535/early_setup.c
index 1a612cc55f..4a2e1b4965 100644
--- a/src/southbridge/amd/cs5535/early_setup.c
+++ b/src/southbridge/amd/cs5535/early_setup.c
@@ -107,15 +107,11 @@ static void cs5535_setup_cis_mode(void)
{
msr_t msr;
- /* setup CPU interface serial to mode C on both sides */
+ /* Setup CPU serial SouthBridge interface to mode C. */
msr = rdmsr(GLPCI_SB_CTRL);
msr.lo &= ~0x18;
msr.lo |= 0x10;
wrmsr(GLPCI_SB_CTRL, msr);
- //Only do this if we are building for 5535
- msr.lo = 0x2;
- msr.hi = 0x0;
- wrmsr(VIP_GIO_MSR_SEL, msr);
}
static void dummy(void)
diff --git a/src/southbridge/amd/cs5536/early_setup.c b/src/southbridge/amd/cs5536/early_setup.c
index 0a35964ef2..7d982433d4 100644
--- a/src/southbridge/amd/cs5536/early_setup.c
+++ b/src/southbridge/amd/cs5536/early_setup.c
@@ -145,7 +145,7 @@ static void cs5536_setup_cis_mode(void)
{
msr_t msr;
- /* setup CPU interface serial to mode B to match CPU */
+ /* Setup CPU serial SouthBridge interface to mode C. */
msr = rdmsr(GLPCI_SB_CTRL);
msr.lo &= ~0x18;
msr.lo |= 0x10;