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authorDuncan Laurie <dlaurie@chromium.org>2015-08-27 16:53:45 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-09-08 11:18:30 +0000
commit86f23acee5e9945efe1aaf99dd6dc9deb6554b11 (patch)
tree9022c367423a92e79e16bcf061b60ee0054469b5 /src
parent9171f1ab8d9164f909f794a8a308a944ddefc74d (diff)
downloadcoreboot-86f23acee5e9945efe1aaf99dd6dc9deb6554b11.tar.xz
skylake: ACPI: Move storage controllers to separate file
Move the storage controller devices out of serialio.asl and into a new scs.asl file and implement the power gating workarounds for D0 and D3 transitions. BUG=chrome-os-partner:44622 BRANCH=none TEST=emerge-glados coreboot Change-Id: I43081e661b7220bfa635c2d166c3675a0ff910d6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e0c67b386974dedf7ad475c174c0bc75dc27e529 Original-Change-Id: Iadb395f152905f210ab0361121bbd69c9731c084 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295908 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11535 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/skylake/acpi/pch.asl2
-rw-r--r--src/soc/intel/skylake/acpi/scs.asl125
-rw-r--r--src/soc/intel/skylake/acpi/serialio.asl29
3 files changed, 127 insertions, 29 deletions
diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl
index c72a704fc4..f2c1a16d04 100644
--- a/src/soc/intel/skylake/acpi/pch.asl
+++ b/src/soc/intel/skylake/acpi/pch.asl
@@ -46,6 +46,8 @@
/* SMBus 0:1f.3 */
#include "smbus.asl"
+/* Storage Controllers */
+#include "scs.asl"
/* USB XHCI 0:14.0 */
#include "xhci.asl"
diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl
new file mode 100644
index 0000000000..4eb9683c7d
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/scs.asl
@@ -0,0 +1,125 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* Intel Storage Controllers */
+
+Device (EMMC)
+{
+ Name (_ADR, 0x001E0004)
+ Name (_DDN, "eMMC Controller")
+
+ OperationRegion (EMCR, PCI_Config, 0x00, 0x100)
+ Field (EMCR, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x84), /* PMECTRLSTATUS */
+ D0D3, 2, /* POWERSTATE */
+ Offset (0xa2), /* PG_CONFIG */
+ , 2,
+ PGEN, 1, /* PG_ENABLE */
+ }
+
+ Method (_PS0, 0, Serialized)
+ {
+ /* Disable Power Good */
+ Store (0, ^PGEN)
+
+ /* Clear bits 31, 6, 2, 0 */
+ ^^PCRA (PID_SCS, 0x600, 0x7FFFFFBA)
+ Sleep (2)
+
+ /* Set bits 31, 6, 2, 0 */
+ ^^PCRO (PID_SCS, 0x600, 0x80000045)
+
+ /* Set Power State to D0 */
+ Store (0, ^D0D3)
+ Store (^D0D3, Local0)
+ }
+
+ Method (_PS3, 0, Serialized)
+ {
+ /* Enable Power Good */
+ Store (1, ^PGEN)
+
+ /* Set Power State to D0 */
+ Store (3, ^D0D3)
+ Store (^D0D3, Local0)
+ }
+
+ Device (CARD)
+ {
+ Name (_ADR, 0x00000008)
+ Method (_RMV, 0, NotSerialized)
+ {
+ Return (0)
+ }
+ }
+}
+
+Device (SDXC)
+{
+ Name (_ADR, 0x001E0006)
+ Name (_DDN, "SD Controller")
+
+ OperationRegion (SDCR, PCI_Config, 0x00, 0x100)
+ Field (SDCR, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x84), /* PMECTRLSTATUS */
+ D0D3, 2, /* POWERSTATE */
+ Offset (0xa2), /* PG_CONFIG */
+ , 2,
+ PGEN, 1, /* PG_ENABLE */
+ }
+
+ Method (_PS0, 0, Serialized)
+ {
+ /* Disable Power Good */
+ Store (0, ^PGEN)
+
+ /* Clear bits 8, 7, 2, 0 */
+ ^^PCRA (PID_SCS, 0x600, 0xFFFFFE7A)
+ Sleep (2)
+
+ /* Set bits 31, 6, 2, 0 */
+ ^^PCRO (PID_SCS, 0x600, 0x00000185)
+
+ /* Set Power State to D0 */
+ Store (0, ^D0D3)
+ Store (^D0D3, Local0)
+ }
+
+ Method (_PS3, 0, Serialized)
+ {
+ /* Enable Power Good */
+ Store (1, ^PGEN)
+
+ /* Set Power State to D0 */
+ Store (3, ^D0D3)
+ Store (^D0D3, Local0)
+ }
+
+ Device (CARD)
+ {
+ Name (_ADR, 0x00000008)
+ Method (_RMV, 0, NotSerialized)
+ {
+ Return (1)
+ }
+ }
+}
diff --git a/src/soc/intel/skylake/acpi/serialio.asl b/src/soc/intel/skylake/acpi/serialio.asl
index e57b937824..d3dca7fb14 100644
--- a/src/soc/intel/skylake/acpi/serialio.asl
+++ b/src/soc/intel/skylake/acpi/serialio.asl
@@ -618,32 +618,3 @@ Device (UAR2)
^^LPD3 (\SAB1, \SAEN)
}
}
-
-
-Device (PEMC)
-{
- Name (_ADR, 0x001E0004)
- Device (CARD)
- {
- Name (_ADR, 0x00000008)
- Method (_RMV, 0x0, NotSerialized)
- {
- Return (0)
- }
- }
-}
-
-/* SD controller */
-Device (PSDC)
-{
- Name (_ADR, 0x001E0006)
- Device (CARD)
- {
- Name (_ADR, 0x00000008)
- Method (_RMV, 0x0, NotSerialized)
- {
- Return (1)
- }
- }
-}
-