src/mainboard: Capitalize ROM, RAM, CPU and APIC

Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15987
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

126 files changed, 173 insertions, 173 deletions

diff --git a/src/mainboard/amd/db-ft3b-lc/Makefile.inc b/src/mainboard/amd/db-ft3b-lc/Makefile.inc
index 8b160e26f4..97c761fa45 100644
--- a/src/mainboard/amd/db-ft3b-lc/Makefile.inc
+++ b/src/mainboard/amd/db-ft3b-lc/Makefile.inc
@@ -27,7 +27,7 @@ SPD_SOURCES  = Memphis_MEM4G16D3EABG
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/amd/db800/irq_tables.c b/src/mainboard/amd/db800/irq_tables.c
index 00a19dba66..8cf172a540 100644
--- a/src/mainboard/amd/db800/irq_tables.c
+++ b/src/mainboard/amd/db800/irq_tables.c
@@ -52,7 +52,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	{
 	 /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
 	 /* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
-	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* cpu */
+	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* CPU */
 	 {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},	/* chipset */
 	 {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* ethernet */
 	 {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0},	/* slot1 */
diff --git a/src/mainboard/amd/dbm690t/fadt.c b/src/mainboard/amd/dbm690t/fadt.c
index 4afb0b9e4c..f9768b20bd 100644
--- a/src/mainboard/amd/dbm690t/fadt.c
+++ b/src/mainboard/amd/dbm690t/fadt.c
@@ -25,7 +25,7 @@
 #include "southbridge/amd/sb600/sb600.h"
 
 /*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
 /* pm_base should be got from bar2 of rs690. Here I compact ACPI
  * registers into 32 bytes limit.
  * */
diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c
index 3fd9c48885..e237ff0b79 100644
--- a/src/mainboard/amd/dinar/buildOpts.c
+++ b/src/mainboard/amd/dinar/buildOpts.c
@@ -54,10 +54,10 @@
 #define POWER_DOWN_BY_CHANNEL		0	///< Channel power down mode
 #define POWER_DOWN_BY_CHIP_SELECT	1	///< Chip select power down mode
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  TRUE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index 70cd5e3586..bc5d3126f2 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -94,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 
 	post_code(0x43);
-	printk(BIOS_DEBUG, "Disabling cache as ram ");
+	printk(BIOS_DEBUG, "Disabling cache as RAM ");
 	disable_cache_as_ram();
 	printk(BIOS_DEBUG, "done\n");
 
diff --git a/src/mainboard/amd/f2950/irq_tables.c b/src/mainboard/amd/f2950/irq_tables.c
index b438f0246e..dae29a142f 100644
--- a/src/mainboard/amd/f2950/irq_tables.c
+++ b/src/mainboard/amd/f2950/irq_tables.c
@@ -52,7 +52,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	{
 	 /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
 	 /* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
-	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* cpu */
+	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* CPU */
 	 {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
 	 {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},   /* ethernet */
 	 }
diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c
index 361531e612..1c5c424fdd 100644
--- a/src/mainboard/amd/inagua/buildOpts.c
+++ b/src/mainboard/amd/inagua/buildOpts.c
@@ -30,13 +30,13 @@
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/* Select the cpu family. */
+/* Select the CPU family. */
 #define INSTALL_FAMILY_10_SUPPORT		FALSE
 #define INSTALL_FAMILY_12_SUPPORT		FALSE
 #define INSTALL_FAMILY_14_SUPPORT		TRUE
 #define INSTALL_FAMILY_15_SUPPORT		FALSE
 
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
 #define INSTALL_G34_SOCKET_SUPPORT		FALSE
 #define INSTALL_C32_SOCKET_SUPPORT 		FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT		FALSE
diff --git a/src/mainboard/amd/norwich/irq_tables.c b/src/mainboard/amd/norwich/irq_tables.c
index dfb1ef4d08..a59dc26df7 100644
--- a/src/mainboard/amd/norwich/irq_tables.c
+++ b/src/mainboard/amd/norwich/irq_tables.c
@@ -52,7 +52,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	{
 	 /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
 	 /* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
-	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* cpu */
+	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* CPU */
 	 {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},	/* chipset */
 	 {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0},	/* slot1 */
 	 {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0},	/* slot2 */
diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c
index 25cec3b0b6..8ba3c539ba 100644
--- a/src/mainboard/amd/parmer/buildOpts.c
+++ b/src/mainboard/amd/parmer/buildOpts.c
@@ -30,13 +30,13 @@
 #include "Filecode.h"
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT FALSE
 #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c
index eb6cf33fa4..670010d4c9 100644
--- a/src/mainboard/amd/persimmon/buildOpts.c
+++ b/src/mainboard/amd/persimmon/buildOpts.c
@@ -30,13 +30,13 @@
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/*	Select the cpu family.	*/
+/*	Select the CPU family.	*/
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT TRUE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/*	Select the cpu socket type.	*/
+/*	Select the CPU socket type.	*/
 #define INSTALL_G34_SOCKET_SUPPORT	FALSE
 #define INSTALL_C32_SOCKET_SUPPORT	FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/pistachio/fadt.c b/src/mainboard/amd/pistachio/fadt.c
index 4afb0b9e4c..f9768b20bd 100644
--- a/src/mainboard/amd/pistachio/fadt.c
+++ b/src/mainboard/amd/pistachio/fadt.c
@@ -25,7 +25,7 @@
 #include "southbridge/amd/sb600/sb600.h"
 
 /*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
 /* pm_base should be got from bar2 of rs690. Here I compact ACPI
  * registers into 32 bytes limit.
  * */
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl
index cc9b65bfc9..aaa778b7ee 100644
--- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl
+++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl
@@ -61,7 +61,7 @@
 
             Device (SBC3)
             {
-                /*  acpi smbus   it should be 0x00040003 if 8131 present */
+                /*  ACPI smbus   it should be 0x00040003 if 8131 present */
 		Method (_ADR, 0, NotSerialized)
 		{
 			Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
diff --git a/src/mainboard/amd/serengeti_cheetah/fadt.c b/src/mainboard/amd/serengeti_cheetah/fadt.c
index 4fe4efd0ce..bd0096152b 100644
--- a/src/mainboard/amd/serengeti_cheetah/fadt.c
+++ b/src/mainboard/amd/serengeti_cheetah/fadt.c
@@ -21,7 +21,7 @@
 #include <console/console.h>
 #include <arch/acpi.h>
 
-extern unsigned pm_base; /* pm_base should be set in sb acpi */
+extern unsigned pm_base; /* pm_base should be set in sb ACPI */
 
 void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
 
diff --git a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
index 0492e9a5c5..1eb97b59a7 100644
--- a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
+++ b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
@@ -77,7 +77,7 @@ static unsigned get_hcid(unsigned i)
 
 	// we may need more way to find out hcid: subsystem id? GPIO read ?
 
-	// we need use id for 1. bus num, 2. mptable, 3. acpi table
+	// we need use id for 1. bus num, 2. mptable, 3. ACPI table
 
 	return id;
 }
diff --git a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt b/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
index b999dfacbf..0dbf303935 100644
--- a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
+++ b/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
@@ -1,4 +1,4 @@
-At this time, For acpi support We got
+At this time, For ACPI support We got
 1. support AMK K8 SRAT --- dynamically (coreboot run-time)  (src/northbridge/amd/amdk8/amdk8_acpi.c)
 2. support MADT ---- dynamically (coreboot run-time)  (src/northbridge/amd/amdk8/amdk8_acpi.c , src/mainboard/amd/serengeti_cheetah/acpi_tables.c)
 3. support DSDT ---- dynamically (Compile time, coreboot run-time, ACPI run-time) (src/mainboard/amd/serengeti_cheetah/{acpi/*, get_bus_conf.c}, src/northbridge/amd/amdk8/get_sblk_pci1234.c)
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index ded74a5e25..51fce316a7 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -224,5 +224,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
 #endif
 
-        post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+        post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
 }
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111.asl b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111.asl
index 46fe1216b8..f6a1954aa1 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111.asl
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111.asl
@@ -53,7 +53,7 @@
 
 	Device (SBC3)
 	{
-		// acpi smbus it should be 0x00040003 if 8131 present
+		// ACPI smbus it should be 0x00040003 if 8131 present
 		Method (_ADR, 0, NotSerialized)
 		{
 			Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c
index 544df8ef8f..3183a7ebcc 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c
@@ -24,7 +24,7 @@
 #include <console/console.h>
 #include <arch/acpi.h>
 
-extern u32 pm_base; /* pm_base should be set in sb acpi */
+extern u32 pm_base; /* pm_base should be set in sb ACPI */
 
 void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
 
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
index 6113f0e097..66dee1831d 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
@@ -81,7 +81,7 @@ static u32 get_hcid(u32 i)
 		break;
 	}
 	// we may need more way to find out hcid: subsystem id? GPIO read ?
-	// we need use id for 1. bus num, 2. mptable, 3. acpi table
+	// we need use id for 1. bus num, 2. mptable, 3. ACPI table
 	return id;
 }
 
diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c
index 2b411e7792..38a272d6d7 100644
--- a/src/mainboard/amd/south_station/buildOpts.c
+++ b/src/mainboard/amd/south_station/buildOpts.c
@@ -30,13 +30,13 @@
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT TRUE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c
index 4da5f5f266..8ed3bf2fdc 100644
--- a/src/mainboard/amd/thatcher/buildOpts.c
+++ b/src/mainboard/amd/thatcher/buildOpts.c
@@ -30,13 +30,13 @@
 #include "Filecode.h"
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT FALSE
 #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c
index e0ee622dbf..d81748af92 100644
--- a/src/mainboard/amd/torpedo/buildOpts.c
+++ b/src/mainboard/amd/torpedo/buildOpts.c
@@ -31,13 +31,13 @@
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT TRUE
 #define INSTALL_FAMILY_14_SUPPORT FALSE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c
index 9a615c119b..fba8fc83cd 100644
--- a/src/mainboard/amd/torpedo/fadt.c
+++ b/src/mainboard/amd/torpedo/fadt.c
@@ -27,7 +27,7 @@
 #include "SbPlatform.h"
 
 /*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
 /* pm_base should be got from bar2 of sb900. Here I compact ACPI
  * registers into 32 bytes limit.
  * */
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
index bf551a9ffc..c5c908de9c 100644
--- a/src/mainboard/amd/torpedo/mptable.c
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -77,7 +77,7 @@ static void *smp_write_config_table(void *v)
   mptable_init(mc, LOCAL_APIC_ADDR);
   memcpy(mc->mpc_oem, "AMD     ", 8);
 
-  /*Inagua used dure core cpu with one die */
+  /*Inagua used dure core CPU with one die */
   boot_apic_id = lapicid();
   apic_version = lapic_read(LAPIC_LVR) & 0xff;
   result = cpuid(1);
diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c
index 2b411e7792..38a272d6d7 100644
--- a/src/mainboard/amd/union_station/buildOpts.c
+++ b/src/mainboard/amd/union_station/buildOpts.c
@@ -30,13 +30,13 @@
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT TRUE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/apple/macbook21/cmos.layout b/src/mainboard/apple/macbook21/cmos.layout
index c11997cff1..a64834581f 100644
--- a/src/mainboard/apple/macbook21/cmos.layout
+++ b/src/mainboard/apple/macbook21/cmos.layout
@@ -72,7 +72,7 @@ entries
 984         16       h       0        check_sum
 #1000        24       r       0        amd_reserved
 
-# ram initialization internal data
+# RAM initialization internal data
 1024         8       r       0        C0WL0REOST
 1032         8       r       0        C1WL0REOST
 1040         8       r       0        RCVENMT
diff --git a/src/mainboard/artecgroup/dbe61/irq_tables.c b/src/mainboard/artecgroup/dbe61/irq_tables.c
index 7adac7e20a..e1af4d7ff1 100644
--- a/src/mainboard/artecgroup/dbe61/irq_tables.c
+++ b/src/mainboard/artecgroup/dbe61/irq_tables.c
@@ -52,7 +52,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	{
 	 /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
 	 /* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
-	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* cpu */
+	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* CPU */
 	 {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},	/* chipset */
 	 {0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* ethernet */
 	 }
diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c
index 2d49af2454..bdda82e1f4 100644
--- a/src/mainboard/asrock/e350m1/buildOpts.c
+++ b/src/mainboard/asrock/e350m1/buildOpts.c
@@ -31,13 +31,13 @@
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT TRUE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c
index ec60a22c8d..e0a1ea4d3a 100644
--- a/src/mainboard/asus/f2a85-m/buildOpts.c
+++ b/src/mainboard/asus/f2a85-m/buildOpts.c
@@ -43,13 +43,13 @@
 
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT FALSE
 #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/asus/f2a85-m_le/buildOpts.c b/src/mainboard/asus/f2a85-m_le/buildOpts.c
index 6110c23ad4..88ff778446 100644
--- a/src/mainboard/asus/f2a85-m_le/buildOpts.c
+++ b/src/mainboard/asus/f2a85-m_le/buildOpts.c
@@ -43,13 +43,13 @@
 
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT FALSE
 #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/asus/kcma-d8/resourcemap.c b/src/mainboard/asus/kcma-d8/resourcemap.c
index f7a2133867..937f4b7552 100644
--- a/src/mainboard/asus/kcma-d8/resourcemap.c
+++ b/src/mainboard/asus/kcma-d8/resourcemap.c
@@ -196,7 +196,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of cpu 0 --> AMD SR5690 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of CPU 0 --> AMD SR5690 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -267,7 +267,7 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of cpu 0 --> AMD SR5690 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of CPU 0 --> AMD SR5690 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
@@ -451,7 +451,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of cpu 0 --> AMD SR5690 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of CPU 0 --> AMD SR5690 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -522,7 +522,7 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of cpu 0 --> AMD SR5690 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of CPU 0 --> AMD SR5690 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c
index 3f96c52ff7..e06e02b95c 100644
--- a/src/mainboard/asus/kcma-d8/romstage.c
+++ b/src/mainboard/asus/kcma-d8/romstage.c
@@ -532,7 +532,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x3B);
 
-	/* Wait for all APs to be stopped, otherwise ram initialization may hang */
+	/* Wait for all APs to be stopped, otherwise RAM initialization may hang */
 	if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
 		wait_all_other_cores_stopped(bsp_apicid);
 
diff --git a/src/mainboard/asus/kfsn4-dre/resourcemap.c b/src/mainboard/asus/kfsn4-dre/resourcemap.c
index 3718dfdf7b..cfbade68f2 100644
--- a/src/mainboard/asus/kfsn4-dre/resourcemap.c
+++ b/src/mainboard/asus/kfsn4-dre/resourcemap.c
@@ -196,7 +196,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of cpu 0 --> Nvidia CK 804 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> Nvidia CK 804 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -267,7 +267,7 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of cpu 0 --> Nvidia CK 804 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> Nvidia CK 804 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c b/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c
index 3718dfdf7b..cfbade68f2 100644
--- a/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c
+++ b/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c
@@ -196,7 +196,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of cpu 0 --> Nvidia CK 804 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> Nvidia CK 804 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -267,7 +267,7 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of cpu 0 --> Nvidia CK 804 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> Nvidia CK 804 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/asus/kgpe-d16/resourcemap.c b/src/mainboard/asus/kgpe-d16/resourcemap.c
index 8bcb28ba58..d1fcad7d5a 100644
--- a/src/mainboard/asus/kgpe-d16/resourcemap.c
+++ b/src/mainboard/asus/kgpe-d16/resourcemap.c
@@ -196,7 +196,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of cpu 0 --> AMD SR5690 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> AMD SR5690 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -267,7 +267,7 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of cpu 0 --> AMD SR5690 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> AMD SR5690 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
@@ -451,7 +451,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff110, /* link 3 of cpu 0 --> AMD SR5690 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff110, /* link 3 of CPU 0 --> AMD SR5690 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -522,7 +522,7 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000303, /* link 3 of cpu 0 --> AMD SR5690 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000303, /* link 3 of CPU 0 --> AMD SR5690 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
index fd3411a2e7..e5550bd8c6 100644
--- a/src/mainboard/asus/kgpe-d16/romstage.c
+++ b/src/mainboard/asus/kgpe-d16/romstage.c
@@ -573,7 +573,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x3B);
 
-	/* Wait for all APs to be stopped, otherwise ram initialization may hang */
+	/* Wait for all APs to be stopped, otherwise RAM initialization may hang */
 	if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
 		wait_all_other_cores_stopped(bsp_apicid);
 
diff --git a/src/mainboard/asus/m2n-e/resourcemap.c b/src/mainboard/asus/m2n-e/resourcemap.c
index 784fe0ffb0..57e7389490 100644
--- a/src/mainboard/asus/m2n-e/resourcemap.c
+++ b/src/mainboard/asus/m2n-e/resourcemap.c
@@ -265,7 +265,7 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */
+//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
 		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl
index b97ba40540..00bea29e17 100644
--- a/src/mainboard/asus/p2b/dsdt.asl
+++ b/src/mainboard/asus/p2b/dsdt.asl
@@ -28,7 +28,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE  ", "COREBOOT", 1)
 	 * 3: powered on suspend, CPU context lost			S1
 	 *    Note: Looks like 'CPU context lost' does _not_ mean the
 	 *          CPU restarts at the reset vector. Most likely only
-	 *          caches are lost, so both 0x3 and 0x4 map to acpi S1
+	 *          caches are lost, so both 0x3 and 0x4 map to ACPI S1
 	 * 4: powered on suspend, context maintained			S1
 	 * 5: working (clock control)					S0
 	 * 6: reserved
diff --git a/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex b/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex
index 507c9f1174..51e3501067 100644
--- a/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex
+++ b/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex
@@ -15,7 +15,7 @@
 # GNU General Public License for more details.
 
 # Memory chip: Hynix H5TQ4G63MFR-PBC with ECC
-# BAP ODE E21XX has 2GB ram soldered down on the Q7
+# BAP ODE E21XX has 2GB RAM soldered down on the Q7
 # Memory setting for DDR-1066
 
 #	0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
diff --git a/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex b/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex
index 1991f84fb2..7949ce81b9 100644
--- a/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex
+++ b/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex
@@ -15,7 +15,7 @@
 # GNU General Public License for more details.
 
 # Memory chip: Hynix H5TQ4G63MFR-PBC with ECC
-# BAP ODE E21XX has 2GB ram soldered down on the Q7
+# BAP ODE E21XX has 2GB RAM soldered down on the Q7
 # Memory setting for DDR-1333
 
 #	0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
diff --git a/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex b/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex
index e657179405..6653aa43b4 100644
--- a/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex
+++ b/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex
@@ -15,7 +15,7 @@
 # GNU General Public License for more details.
 
 # Memory chip: Hynix H5TQ4G63MFR-PBC with ECC
-# BAP ODE E21XX has 2GB ram soldered down on the Q7
+# BAP ODE E21XX has 2GB RAM soldered down on the Q7
 # Memory setting for DDR-800
 
 #	0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
diff --git a/src/mainboard/bap/ode_e21XX/Makefile.inc b/src/mainboard/bap/ode_e21XX/Makefile.inc
index 4f4a11d7ce..b0ce62781a 100644
--- a/src/mainboard/bap/ode_e21XX/Makefile.inc
+++ b/src/mainboard/bap/ode_e21XX/Makefile.inc
@@ -27,7 +27,7 @@ SPD_SOURCES  = BAP_Q7_800 BAP_Q7_1066 BAP_Q7_1333
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/emulation/qemu-armv7/media.c b/src/mainboard/emulation/qemu-armv7/media.c
index 71f3c75ef3..27c3af15c0 100644
--- a/src/mainboard/emulation/qemu-armv7/media.c
+++ b/src/mainboard/emulation/qemu-armv7/media.c
@@ -14,7 +14,7 @@
  */
 #include <boot_device.h>
 
-/* Maps directly to NOR flash up to rom size. */
+/* Maps directly to NOR flash up to ROM size. */
 static const struct mem_region_device boot_dev =
 	MEM_REGION_DEV_RO_INIT((void *)0x0, CONFIG_ROM_SIZE);
 
diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl b/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl
index 0f3e83b14d..17e166ce36 100644
--- a/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl
+++ b/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl
@@ -43,7 +43,7 @@ Scope(\_SB) {
         PRS, 256
     }
     Method(PRSC, 0) {
-        // Local5 = active cpu bitmap
+        // Local5 = active CPU bitmap
         Store(PRS, Local5)
         // Local2 = last read byte from bitmap
         Store(Zero, Local2)
@@ -56,7 +56,7 @@ Scope(\_SB) {
                 // Shift down previously read bitmap byte
                 ShiftRight(Local2, 1, Local2)
             } Else {
-                // Read next byte from cpu bitmap
+                // Read next byte from CPU bitmap
                 Store(DerefOf(Index(Local5, ShiftRight(Local0, 3))), Local2)
             }
             // Local3 = active state for this cpu
diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c
index 9f6a55ce97..565b85585c 100644
--- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c
+++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c
@@ -118,21 +118,21 @@ int fw_cfg_max_cpus(void)
 /* ---------------------------------------------------------------------- */
 
 /*
- * Starting with release 1.7 qemu provides acpi tables via fw_cfg.
+ * Starting with release 1.7 qemu provides ACPI tables via fw_cfg.
  * Main advantage is that new (virtual) hardware which needs acpi
  * support JustWorks[tm] without having to patch & update the firmware
  * (seabios, coreboot, ...) accordingly.
  *
  * Qemu provides a etc/table-loader file with instructions for the
  * firmware:
- *   - A "load" instruction to fetch acpi data from fw_cfg.
+ *   - A "load" instruction to fetch ACPI data from fw_cfg.
  *   - A "pointer" instruction to patch a pointer.  This is needed to
  *     get table-to-table references right, it is basically a
- *     primitive dynamic linker for acpi tables.
- *   - A "checksum" instruction to generate acpi table checksums.
+ *     primitive dynamic linker for ACPI tables.
+ *   - A "checksum" instruction to generate ACPI table checksums.
  *
  * If a etc/table-loader file is found we'll go try loading the acpi
- * tables from fw_cfg, otherwise we'll fallback to the acpi tables
+ * tables from fw_cfg, otherwise we'll fallback to the ACPI tables
  * compiled in.
  */
 
@@ -211,7 +211,7 @@ unsigned long fw_cfg_acpi_tables(unsigned long start)
 	if (rc < 0)
 		return 0;
 
-	printk(BIOS_DEBUG, "QEMU: found acpi tables in fw_cfg.\n");
+	printk(BIOS_DEBUG, "QEMU: found ACPI tables in fw_cfg.\n");
 
 	max = rc / sizeof(*s);
 	s = malloc(rc);
@@ -259,7 +259,7 @@ unsigned long fw_cfg_acpi_tables(unsigned long start)
 
 			default:
 				/*
-				 * Should not happen.  acpi knows 1 and 2 byte ptrs
+				 * Should not happen.  ACPI knows 1 and 2 byte ptrs
 				 * too, but we are operating with 32bit offsets which
 				 * would simply not fit in there ...
 				 */
@@ -293,13 +293,13 @@ unsigned long fw_cfg_acpi_tables(unsigned long start)
 		};
 	}
 
-	printk(BIOS_DEBUG, "QEMU: loaded acpi tables from fw_cfg.\n");
+	printk(BIOS_DEBUG, "QEMU: loaded ACPI tables from fw_cfg.\n");
 	free(s);
 	free(addrs);
 	return ALIGN(current, 16);
 
 err:
-	printk(BIOS_DEBUG, "QEMU: loading acpi tables from fw_cfg failed.\n");
+	printk(BIOS_DEBUG, "QEMU: loading ACPI tables from fw_cfg failed.\n");
 	free(s);
 	free(addrs);
 	return 0;
diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c
index 26cbda5a6b..575069cc7e 100644
--- a/src/mainboard/emulation/qemu-i440fx/northbridge.c
+++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c
@@ -72,7 +72,7 @@ static void cpu_pci_domain_read_resources(struct device *dev)
 		fw_cfg_load_file("etc/e820", list);
 		for (i = 0; i < size/sizeof(*list); i++) {
 			switch (list[i].type) {
-			case 1: /* ram */
+			case 1: /* RAM */
 				printk(BIOS_DEBUG, "QEMU: e820/ram: 0x%08llx +0x%08llx\n",
 				       list[i].address, list[i].length);
 				if (list[i].address == 0) {
@@ -135,7 +135,7 @@ static void cpu_pci_domain_read_resources(struct device *dev)
 		 * Reserve the region between top-of-ram and the
 		 * mmconf xbar (ar 0xb0000000), so coreboot doesn't
 		 * place pci bars there.  The region isn't declared as
-		 * pci io window in the acpi tables (\_SB.PCI0._CRS).
+		 * pci io window in the ACPI tables (\_SB.PCI0._CRS).
 		 */
 		res = new_resource(dev, idx++);
 		res->base = tomk * 1024;
diff --git a/src/mainboard/emulation/qemu-power8/mainboard.c b/src/mainboard/emulation/qemu-power8/mainboard.c
index b7a7213d2c..102f54c2ee 100644
--- a/src/mainboard/emulation/qemu-power8/mainboard.c
+++ b/src/mainboard/emulation/qemu-power8/mainboard.c
@@ -26,7 +26,7 @@ static void mainboard_enable(device_t dev)
 			;
 	}
 
-	// Where does ram live?
+	// Where does RAM live?
 	ram_resource(dev, 0, 2048, 32768);
 	cbmem_recovery(0);
 }
diff --git a/src/mainboard/getac/p470/cmos.layout b/src/mainboard/getac/p470/cmos.layout
index 023bdfacab..177bdfe764 100644
--- a/src/mainboard/getac/p470/cmos.layout
+++ b/src/mainboard/getac/p470/cmos.layout
@@ -72,7 +72,7 @@ entries
 984         16       h       0        check_sum
 #1000        24       r       0        amd_reserved
 
-# ram initialization internal data
+# RAM initialization internal data
 1024         8       r       0        C0WL0REOST
 1032         8       r       0        C1WL0REOST
 1040         8       r       0        RCVENMT
diff --git a/src/mainboard/getac/p470/cstates.c b/src/mainboard/getac/p470/cstates.c
index 7a2a3e5771..d70c4fa54f 100644
--- a/src/mainboard/getac/p470/cstates.c
+++ b/src/mainboard/getac/p470/cstates.c
@@ -4,17 +4,17 @@
 
 static acpi_cstate_t cst_entries[] = {
 	{
-		/* acpi C1 / cpu C1 */
+		/* ACPI C1 / CPU C1 */
 		1, 0x01, 1000,
 		{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 }
 	},
 	{
-		/* acpi C2 / cpu C2 */
+		/* ACPI C2 / CPU C2 */
 		2, 0x01,  500,
 		{ ACPI_ADDRESS_SPACE_IO, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 }
 	},
 	{
-		/* acpi C3 / cpu C2 */
+		/* ACPI C3 / CPU C2 */
 		2, 0x11,  250,
 		{ ACPI_ADDRESS_SPACE_IO, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 }
 	},
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c b/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c
index 17b95e1491..35c54c8344 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c
@@ -265,7 +265,7 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */
+//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
 		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 35a5cb442f..8bc71a961a 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -193,5 +193,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
         sis_init_stage2();
-        post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+        post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
 }
diff --git a/src/mainboard/gigabyte/m57sli/resourcemap.c b/src/mainboard/gigabyte/m57sli/resourcemap.c
index 17b95e1491..35c54c8344 100644
--- a/src/mainboard/gigabyte/m57sli/resourcemap.c
+++ b/src/mainboard/gigabyte/m57sli/resourcemap.c
@@ -265,7 +265,7 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */
+//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
 		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index 67bf503baf..b1c849b9bb 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -199,5 +199,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
-        post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+        post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
 }
diff --git a/src/mainboard/gizmosphere/gizmo/Makefile.inc b/src/mainboard/gizmosphere/gizmo/Makefile.inc
index 6d51373c3f..a2a8dadd1e 100644
--- a/src/mainboard/gizmosphere/gizmo/Makefile.inc
+++ b/src/mainboard/gizmosphere/gizmo/Makefile.inc
@@ -37,7 +37,7 @@ SPD_SOURCES  = Elpida_EDJ2116DEBG
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c
index d164e2e711..d891875aa9 100644
--- a/src/mainboard/gizmosphere/gizmo/buildOpts.c
+++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c
@@ -32,13 +32,13 @@
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/*	Select the cpu family.	*/
+/*	Select the CPU family.	*/
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT TRUE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/*	Select the cpu socket type.	*/
+/*	Select the CPU socket type.	*/
 #define INSTALL_G34_SOCKET_SUPPORT	FALSE
 #define INSTALL_C32_SOCKET_SUPPORT	FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/gizmosphere/gizmo2/Makefile.inc b/src/mainboard/gizmosphere/gizmo2/Makefile.inc
index 8fa32da8ec..8a24bea452 100644
--- a/src/mainboard/gizmosphere/gizmo2/Makefile.inc
+++ b/src/mainboard/gizmosphere/gizmo2/Makefile.inc
@@ -30,7 +30,7 @@ SPD_SOURCES  = Micron_MT41J128M16JT
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/auron/spd/Makefile.inc b/src/mainboard/google/auron/spd/Makefile.inc
index 507bf0cf5e..1695871f2a 100644
--- a/src/mainboard/google/auron/spd/Makefile.inc
+++ b/src/mainboard/google/auron/spd/Makefile.inc
@@ -29,7 +29,7 @@ SPD_SOURCES += empty                    # 0b0111
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/auron_paine/spd/Makefile.inc b/src/mainboard/google/auron_paine/spd/Makefile.inc
index 7846c84f68..6350fc98a1 100644
--- a/src/mainboard/google/auron_paine/spd/Makefile.inc
+++ b/src/mainboard/google/auron_paine/spd/Makefile.inc
@@ -42,7 +42,7 @@ SPD_SOURCES += empty                    # 0b1111
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.xxd)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do xxd -rg1 $$f; \
diff --git a/src/mainboard/google/chell/spd/Makefile.inc b/src/mainboard/google/chell/spd/Makefile.inc
index f0aa6de2e4..f78f3f66f6 100644
--- a/src/mainboard/google/chell/spd/Makefile.inc
+++ b/src/mainboard/google/chell/spd/Makefile.inc
@@ -28,7 +28,7 @@ SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF     # 0b0101
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/cyan/spd/Makefile.inc b/src/mainboard/google/cyan/spd/Makefile.inc
index b1cd16d099..dd62025227 100644
--- a/src/mainboard/google/cyan/spd/Makefile.inc
+++ b/src/mainboard/google/cyan/spd/Makefile.inc
@@ -25,7 +25,7 @@ SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/falco/Makefile.inc b/src/mainboard/google/falco/Makefile.inc
index 5c60d4e3e8..34de87a36e 100644
--- a/src/mainboard/google/falco/Makefile.inc
+++ b/src/mainboard/google/falco/Makefile.inc
@@ -36,7 +36,7 @@ SPD_SOURCES += Samsung_M471B5674QH0   # 2GB / CH0 only  (RAM_ID=111)
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/glados/spd/Makefile.inc b/src/mainboard/google/glados/spd/Makefile.inc
index 78e00c1f74..0d6da9ebcc 100644
--- a/src/mainboard/google/glados/spd/Makefile.inc
+++ b/src/mainboard/google/glados/spd/Makefile.inc
@@ -26,7 +26,7 @@ SPD_SOURCES += hynix_dimm_H9CCNNNBLTALAR        # 0b0011
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/lars/spd/Makefile.inc b/src/mainboard/google/lars/spd/Makefile.inc
index 7f49cdb5dc..d6d789e7a0 100644
--- a/src/mainboard/google/lars/spd/Makefile.inc
+++ b/src/mainboard/google/lars/spd/Makefile.inc
@@ -38,7 +38,7 @@ SPD_SOURCES += empty                                    # 0b1111
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc
index b79e4d3952..a25e95c1e4 100644
--- a/src/mainboard/google/link/Makefile.inc
+++ b/src/mainboard/google/link/Makefile.inc
@@ -31,7 +31,7 @@ SPD_SOURCES += micron_4Gb_1600_1.35v_x16
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/ninja/spd/Makefile.inc b/src/mainboard/google/ninja/spd/Makefile.inc
index 9b4e8c13ea..b2552d32b4 100644
--- a/src/mainboard/google/ninja/spd/Makefile.inc
+++ b/src/mainboard/google/ninja/spd/Makefile.inc
@@ -36,7 +36,7 @@ SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/peppy/Makefile.inc b/src/mainboard/google/peppy/Makefile.inc
index 49165adf33..b49f98e121 100644
--- a/src/mainboard/google/peppy/Makefile.inc
+++ b/src/mainboard/google/peppy/Makefile.inc
@@ -35,7 +35,7 @@ SPD_SOURCES += Elpida_EDJ4216EFBG	# 6: 2GB / CH0 + CH1
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/rambi/spd/Makefile.inc b/src/mainboard/google/rambi/spd/Makefile.inc
index 6a19f0febc..85956b0243 100644
--- a/src/mainboard/google/rambi/spd/Makefile.inc
+++ b/src/mainboard/google/rambi/spd/Makefile.inc
@@ -32,7 +32,7 @@ SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/samus/spd/Makefile.inc b/src/mainboard/google/samus/spd/Makefile.inc
index ef122a0e14..c7c8a75b2a 100644
--- a/src/mainboard/google/samus/spd/Makefile.inc
+++ b/src/mainboard/google/samus/spd/Makefile.inc
@@ -37,7 +37,7 @@ SPD_SOURCES += elpida_16        # 0b1111
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8111.asl b/src/mainboard/hp/dl145_g1/acpi/amd8111.asl
index 77389f0062..8de268bd15 100644
--- a/src/mainboard/hp/dl145_g1/acpi/amd8111.asl
+++ b/src/mainboard/hp/dl145_g1/acpi/amd8111.asl
@@ -597,7 +597,7 @@ Device (IDE0) {
 	}
 }
 Device (PMF) {
-	// acpi smbus   it should be 0x00040003 if 8131 present
+	// ACPI smbus   it should be 0x00040003 if 8131 present
 	Method (_ADR, 0, NotSerialized)
 	{
 		Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
diff --git a/src/mainboard/hp/dl145_g1/dsdt.asl b/src/mainboard/hp/dl145_g1/dsdt.asl
index 9e131b5169..8d97c897c9 100644
--- a/src/mainboard/hp/dl145_g1/dsdt.asl
+++ b/src/mainboard/hp/dl145_g1/dsdt.asl
@@ -172,7 +172,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
 			Notify (\_SB.PWRB, 0x02)
 		}
 	}
-	OperationRegion (KSB0, SystemIO, 0x72, 0x02) // CMOS ram (?)
+	OperationRegion (KSB0, SystemIO, 0x72, 0x02) // CMOS RAM (?)
 	Field (KSB0, ByteAcc, NoLock, Preserve) {
 		KSBI,   8, // Index
 		KSBD,   8  // Data
diff --git a/src/mainboard/hp/dl145_g1/fadt.c b/src/mainboard/hp/dl145_g1/fadt.c
index b81caee018..fb0c62b18e 100644
--- a/src/mainboard/hp/dl145_g1/fadt.c
+++ b/src/mainboard/hp/dl145_g1/fadt.c
@@ -8,7 +8,7 @@
 #include <console/console.h>
 #include <arch/acpi.h>
 
-extern unsigned pm_base; /* pm_base should be set in sb acpi */
+extern unsigned pm_base; /* pm_base should be set in sb ACPI */
 
 void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
 
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
index 37fd521f39..48258ca980 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
@@ -45,13 +45,13 @@
 
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT FALSE
 #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/ibase/mb899/cmos.layout b/src/mainboard/ibase/mb899/cmos.layout
index 5a28952c0a..f42dd0a899 100644
--- a/src/mainboard/ibase/mb899/cmos.layout
+++ b/src/mainboard/ibase/mb899/cmos.layout
@@ -82,7 +82,7 @@ entries
 984         16       h       0        check_sum
 #1000        24       r       0        amd_reserved
 
-# ram initialization internal data
+# RAM initialization internal data
 1024         8       r       0        C0WL0REOST
 1032         8       r       0        C1WL0REOST
 1040         8       r       0        RCVENMT
diff --git a/src/mainboard/intel/d945gclf/cmos.layout b/src/mainboard/intel/d945gclf/cmos.layout
index 31f2b20fa2..c280627af6 100644
--- a/src/mainboard/intel/d945gclf/cmos.layout
+++ b/src/mainboard/intel/d945gclf/cmos.layout
@@ -68,7 +68,7 @@ entries
 984         16       h       0        check_sum
 #1000        24       r       0        amd_reserved
 
-# ram initialization internal data
+# RAM initialization internal data
 1024         8       r       0        C0WL0REOST
 1032         8       r       0        C1WL0REOST
 1040         8       r       0        RCVENMT
diff --git a/src/mainboard/intel/kunimitsu/spd/Makefile.inc b/src/mainboard/intel/kunimitsu/spd/Makefile.inc
index 69446643fa..62d6fd4182 100644
--- a/src/mainboard/intel/kunimitsu/spd/Makefile.inc
+++ b/src/mainboard/intel/kunimitsu/spd/Makefile.inc
@@ -38,7 +38,7 @@ SPD_SOURCES += empty                                    # 0b1111
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/iwave/iWRainbowG6/cmos.layout b/src/mainboard/iwave/iWRainbowG6/cmos.layout
index 0b1845eb43..e2ff2c5128 100644
--- a/src/mainboard/iwave/iWRainbowG6/cmos.layout
+++ b/src/mainboard/iwave/iWRainbowG6/cmos.layout
@@ -75,7 +75,7 @@ entries
 984         16       h       0        check_sum
 #1000        24       r       0        amd_reserved
 
-# ram initialization internal data
+# RAM initialization internal data
 1024         8       r       0        C0WL0REOST
 1032         8       r       0        C1WL0REOST
 1040         8       r       0        RCVENMT
diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl
index 4d41c6079a..df722f8862 100644
--- a/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl
+++ b/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl
@@ -49,7 +49,7 @@
 
             Device (SBC3)
             {
-                /*  acpi smbus   it should be 0x00040003 if 8131 present */
+                /*  ACPI smbus   it should be 0x00040003 if 8131 present */
 		Method (_ADR, 0, NotSerialized)
 		{
 			Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
diff --git a/src/mainboard/iwill/dk8_htx/fadt.c b/src/mainboard/iwill/dk8_htx/fadt.c
index f677b4e8b2..43d7c16ff8 100644
--- a/src/mainboard/iwill/dk8_htx/fadt.c
+++ b/src/mainboard/iwill/dk8_htx/fadt.c
@@ -7,7 +7,7 @@
 #include <console/console.h>
 #include <arch/acpi.h>
 
-extern unsigned pm_base; /* pm_base should be set in sb acpi */
+extern unsigned pm_base; /* pm_base should be set in sb ACPI */
 
 void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
 
diff --git a/src/mainboard/iwill/dk8_htx/get_bus_conf.c b/src/mainboard/iwill/dk8_htx/get_bus_conf.c
index 19255fafcd..25dcab1ab3 100644
--- a/src/mainboard/iwill/dk8_htx/get_bus_conf.c
+++ b/src/mainboard/iwill/dk8_htx/get_bus_conf.c
@@ -64,7 +64,7 @@ static unsigned get_hcid(unsigned i)
 
 	// we may need more way to find out hcid: subsystem id? GPIO read ?
 
-	// we need use id for 1. bus num, 2. mptable, 3. acpi table
+	// we need use id for 1. bus num, 2. mptable, 3. ACPI table
 
 	return id;
 }
diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c
index 9b5b38db72..4cf89b1703 100644
--- a/src/mainboard/iwill/dk8_htx/romstage.c
+++ b/src/mainboard/iwill/dk8_htx/romstage.c
@@ -159,5 +159,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         dump_pci_devices();
 #endif
 
-        post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+        post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
 }
diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
index 79cf695079..390d28ba79 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
@@ -43,13 +43,13 @@
 
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
-/* Select the cpu family. */
+/* Select the CPU family. */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT TRUE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
 #define INSTALL_G34_SOCKET_SUPPORT	FALSE
 #define INSTALL_C32_SOCKET_SUPPORT	FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/kontron/986lcd-m/cmos.layout b/src/mainboard/kontron/986lcd-m/cmos.layout
index f9fb424a5e..2a99e5040a 100644
--- a/src/mainboard/kontron/986lcd-m/cmos.layout
+++ b/src/mainboard/kontron/986lcd-m/cmos.layout
@@ -85,7 +85,7 @@ entries
 984         16       h       0        check_sum
 #1000        24       r       0        amd_reserved
 
-# ram initialization internal data
+# RAM initialization internal data
 1024         8       r       0        C0WL0REOST
 1032         8       r       0        C1WL0REOST
 1040         8       r       0        RCVENMT
diff --git a/src/mainboard/kontron/kt690/fadt.c b/src/mainboard/kontron/kt690/fadt.c
index 4afb0b9e4c..f9768b20bd 100644
--- a/src/mainboard/kontron/kt690/fadt.c
+++ b/src/mainboard/kontron/kt690/fadt.c
@@ -25,7 +25,7 @@
 #include "southbridge/amd/sb600/sb600.h"
 
 /*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
 /* pm_base should be got from bar2 of rs690. Here I compact ACPI
  * registers into 32 bytes limit.
  * */
diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c
index a54b4a85b7..eda1a4d27a 100644
--- a/src/mainboard/lenovo/g505s/buildOpts.c
+++ b/src/mainboard/lenovo/g505s/buildOpts.c
@@ -45,13 +45,13 @@
 
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT FALSE
 #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout
index 03c8683b04..475f4b2914 100644
--- a/src/mainboard/lenovo/t400/cmos.layout
+++ b/src/mainboard/lenovo/t400/cmos.layout
@@ -87,7 +87,7 @@ entries
 984          16       h       0        check_sum
 #1000        24       r       0        unused
 
-# ram initialization internal data
+# RAM initialization internal data
 1024        128       r       0        read_training_results
 
 # -----------------------------------------------------------------
diff --git a/src/mainboard/lenovo/t400/cstates.c b/src/mainboard/lenovo/t400/cstates.c
index 827f76ed8c..3ce2ed1a81 100644
--- a/src/mainboard/lenovo/t400/cstates.c
+++ b/src/mainboard/lenovo/t400/cstates.c
@@ -19,12 +19,12 @@
 
 static acpi_cstate_t cst_entries[] = {
 	{
-		/* acpi C1 / cpu C1 */
+		/* ACPI C1 / CPU C1 */
 		1, 0x01, 1000,
 		{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 }
 	},
 	{
-		/* acpi C2 / cpu C2 */
+		/* ACPI C2 / CPU C2 */
 		2, 0x01,  500,
 		{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 }
 	},
diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout
index e5879d6493..5068fac822 100644
--- a/src/mainboard/lenovo/t60/cmos.layout
+++ b/src/mainboard/lenovo/t60/cmos.layout
@@ -74,7 +74,7 @@ entries
 984         16       h       0        check_sum
 #1000        24       r       0        amd_reserved
 
-# ram initialization internal data
+# RAM initialization internal data
 1024         8       r       0        C0WL0REOST
 1032         8       r       0        C1WL0REOST
 1040         8       r       0        RCVENMT
diff --git a/src/mainboard/lenovo/x200/cmos.layout b/src/mainboard/lenovo/x200/cmos.layout
index a00d703fe6..17918976f5 100644
--- a/src/mainboard/lenovo/x200/cmos.layout
+++ b/src/mainboard/lenovo/x200/cmos.layout
@@ -84,7 +84,7 @@ entries
 984          16       h       0        check_sum
 #1000        24       r       0        unused
 
-# ram initialization internal data
+# RAM initialization internal data
 1024        128       r       0        read_training_results
 
 # -----------------------------------------------------------------
diff --git a/src/mainboard/lenovo/x200/cstates.c b/src/mainboard/lenovo/x200/cstates.c
index 827f76ed8c..3ce2ed1a81 100644
--- a/src/mainboard/lenovo/x200/cstates.c
+++ b/src/mainboard/lenovo/x200/cstates.c
@@ -19,12 +19,12 @@
 
 static acpi_cstate_t cst_entries[] = {
 	{
-		/* acpi C1 / cpu C1 */
+		/* ACPI C1 / CPU C1 */
 		1, 0x01, 1000,
 		{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 }
 	},
 	{
-		/* acpi C2 / cpu C2 */
+		/* ACPI C2 / CPU C2 */
 		2, 0x01,  500,
 		{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 }
 	},
diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout
index 54a279913f..9f10fbc930 100644
--- a/src/mainboard/lenovo/x60/cmos.layout
+++ b/src/mainboard/lenovo/x60/cmos.layout
@@ -74,7 +74,7 @@ entries
 984         16       h       0        check_sum
 #1000        24       r       0        amd_reserved
 
-# ram initialization internal data
+# RAM initialization internal data
 1024         8       r       0        C0WL0REOST
 1032         8       r       0        C1WL0REOST
 1040         8       r       0        RCVENMT
diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c
index 9b03757bdd..30982b5134 100644
--- a/src/mainboard/lippert/frontrunner-af/buildOpts.c
+++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c
@@ -31,13 +31,13 @@
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/*	Select the cpu family.	*/
+/*	Select the CPU family.	*/
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT TRUE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/*	Select the cpu socket type.	*/
+/*	Select the CPU socket type.	*/
 #define INSTALL_G34_SOCKET_SUPPORT	FALSE
 #define INSTALL_C32_SOCKET_SUPPORT	FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c
index 9b03757bdd..30982b5134 100644
--- a/src/mainboard/lippert/toucan-af/buildOpts.c
+++ b/src/mainboard/lippert/toucan-af/buildOpts.c
@@ -31,13 +31,13 @@
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/*	Select the cpu family.	*/
+/*	Select the CPU family.	*/
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT TRUE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/*	Select the cpu socket type.	*/
+/*	Select the CPU socket type.	*/
 #define INSTALL_G34_SOCKET_SUPPORT	FALSE
 #define INSTALL_C32_SOCKET_SUPPORT	FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/msi/ms7260/resourcemap.c b/src/mainboard/msi/ms7260/resourcemap.c
index a7d520d349..f17fadf1a0 100644
--- a/src/mainboard/msi/ms7260/resourcemap.c
+++ b/src/mainboard/msi/ms7260/resourcemap.c
@@ -267,7 +267,7 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */
+//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
 		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/msi/ms9652_fam10/resourcemap.c b/src/mainboard/msi/ms9652_fam10/resourcemap.c
index 76fbaa3803..610baf3631 100644
--- a/src/mainboard/msi/ms9652_fam10/resourcemap.c
+++ b/src/mainboard/msi/ms9652_fam10/resourcemap.c
@@ -269,7 +269,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the highest bus number in configuration region i
 		 */
 		/* Verified against board configuration registers after normal proprietary BIOS boot */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c b/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
index c70cbec87b..b57f957c60 100644
--- a/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
+++ b/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
@@ -79,7 +79,7 @@ static unsigned get_hcid(unsigned i)
 
 	// we may need more way to find out hcid: subsystem id? GPIO read ?
 
-	// we need use id for 1. bus num, 2. mptable, 3. acpi table
+	// we need use id for 1. bus num, 2. mptable, 3. ACPI table
 
 	return id;
 }
diff --git a/src/mainboard/nvidia/l1_2pvv/resourcemap.c b/src/mainboard/nvidia/l1_2pvv/resourcemap.c
index 2950687a75..85782b78da 100644
--- a/src/mainboard/nvidia/l1_2pvv/resourcemap.c
+++ b/src/mainboard/nvidia/l1_2pvv/resourcemap.c
@@ -265,8 +265,8 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */
-//		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */
+//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */
+//		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */
 		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
 
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index 01095f6837..cfe5bebffa 100644
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -185,5 +185,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
-	post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+	post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
 }
diff --git a/src/mainboard/pcengines/apu1/Makefile.inc b/src/mainboard/pcengines/apu1/Makefile.inc
index 97373de9eb..324e4aa365 100644
--- a/src/mainboard/pcengines/apu1/Makefile.inc
+++ b/src/mainboard/pcengines/apu1/Makefile.inc
@@ -39,7 +39,7 @@ SPD_SOURCES  = HYNIX-H5TQ2G83CFR HYNIX-H5TQ4G83MFR
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c
index f7d99c0eae..798b38517e 100644
--- a/src/mainboard/pcengines/apu1/buildOpts.c
+++ b/src/mainboard/pcengines/apu1/buildOpts.c
@@ -30,13 +30,13 @@
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/*	Select the cpu family.	*/
+/*	Select the CPU family.	*/
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT TRUE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/*	Select the cpu socket type.	*/
+/*	Select the CPU socket type.	*/
 #define INSTALL_G34_SOCKET_SUPPORT	FALSE
 #define INSTALL_C32_SOCKET_SUPPORT	FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/roda/rk886ex/cmos.layout b/src/mainboard/roda/rk886ex/cmos.layout
index 023bdfacab..177bdfe764 100644
--- a/src/mainboard/roda/rk886ex/cmos.layout
+++ b/src/mainboard/roda/rk886ex/cmos.layout
@@ -72,7 +72,7 @@ entries
 984         16       h       0        check_sum
 #1000        24       r       0        amd_reserved
 
-# ram initialization internal data
+# RAM initialization internal data
 1024         8       r       0        C0WL0REOST
 1032         8       r       0        C1WL0REOST
 1040         8       r       0        RCVENMT
diff --git a/src/mainboard/roda/rk886ex/m3885.c b/src/mainboard/roda/rk886ex/m3885.c
index 6fd4be986f..6a9b26c6fb 100644
--- a/src/mainboard/roda/rk886ex/m3885.c
+++ b/src/mainboard/roda/rk886ex/m3885.c
@@ -235,7 +235,7 @@ void m3885_configure_multikey(void)
 	u8 reg8;
 	u8 kstate5_flags, offs, maxvars;
 
-	/* ram bank 0 */
+	/* RAM bank 0 */
 	kstate5_flags = m3885_get_variable(0x0c);
 	m3885_set_variable(0x0c, kstate5_flags & ~(7 << 4));
 
@@ -245,7 +245,7 @@ void m3885_configure_multikey(void)
 	}
 
 
-	/* ram bank 2 */
+	/* RAM bank 2 */
 	m3885_set_variable(0x0c, (kstate5_flags & (~(7 << 4))) | (2 << 4));
 
 	/* Get the number of variables */
@@ -254,7 +254,7 @@ void m3885_configure_multikey(void)
 	if (maxvars >= 35) {
 		offs = m3885_get_variable(0x23);
 		if ((offs > 0xc0) || (offs < 0x80)) {
-			printk(BIOS_DEBUG, "M388x does not have a valid ram offset (0x%x)\n", offs);
+			printk(BIOS_DEBUG, "M388x does not have a valid RAM offset (0x%x)\n", offs);
 		} else {
 			printk(BIOS_DEBUG, "Writing Fn-Table to M388x RAM offset 0x%x\n", offs);
 			for (i=0; i < ARRAY_SIZE(function_ram); i++) {
diff --git a/src/mainboard/roda/rk9/cmos.layout b/src/mainboard/roda/rk9/cmos.layout
index c0ea4fc43f..3d757840af 100644
--- a/src/mainboard/roda/rk9/cmos.layout
+++ b/src/mainboard/roda/rk9/cmos.layout
@@ -74,7 +74,7 @@ entries
 
 #1004        20       r       0        unused
 
-# ram initialization internal data
+# RAM initialization internal data
 1024        128       r       0        read_training_results
 
 # -----------------------------------------------------------------
diff --git a/src/mainboard/roda/rk9/cstates.c b/src/mainboard/roda/rk9/cstates.c
index 827f76ed8c..3ce2ed1a81 100644
--- a/src/mainboard/roda/rk9/cstates.c
+++ b/src/mainboard/roda/rk9/cstates.c
@@ -19,12 +19,12 @@
 
 static acpi_cstate_t cst_entries[] = {
 	{
-		/* acpi C1 / cpu C1 */
+		/* ACPI C1 / CPU C1 */
 		1, 0x01, 1000,
 		{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 }
 	},
 	{
-		/* acpi C2 / cpu C2 */
+		/* ACPI C2 / CPU C2 */
 		2, 0x01,  500,
 		{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 }
 	},
diff --git a/src/mainboard/roda/rk9/mainboard.c b/src/mainboard/roda/rk9/mainboard.c
index 8e8f10bf45..395bf4ac28 100644
--- a/src/mainboard/roda/rk9/mainboard.c
+++ b/src/mainboard/roda/rk9/mainboard.c
@@ -24,7 +24,7 @@
 
 static void ec_setup(void)
 {
-	/* Thermal limits?  Values are from ectool's ram dump. */
+	/* Thermal limits?  Values are from ectool's RAM dump. */
 	ec_write(0xd1, 0x57); /* CPUH */
 	ec_write(0xd2, 0xc9); /* CPUL */
 	ec_write(0xd4, 0x64); /* SYSH */
diff --git a/src/mainboard/samsung/lumpy/Makefile.inc b/src/mainboard/samsung/lumpy/Makefile.inc
index 26526c9377..85c5e5804e 100644
--- a/src/mainboard/samsung/lumpy/Makefile.inc
+++ b/src/mainboard/samsung/lumpy/Makefile.inc
@@ -20,7 +20,7 @@ ramstage-y += chromeos.c
 
 SPD_BIN = $(obj)/spd.bin
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN):
 	xxd -rg1 $(src)/mainboard/samsung/lumpy/spd.hex >| $@
 
diff --git a/src/mainboard/siemens/sitemp_g1p1/fadt.c b/src/mainboard/siemens/sitemp_g1p1/fadt.c
index bf06c5d4b9..7d7221d275 100644
--- a/src/mainboard/siemens/sitemp_g1p1/fadt.c
+++ b/src/mainboard/siemens/sitemp_g1p1/fadt.c
@@ -25,7 +25,7 @@
 #include <../southbridge/amd/sb600/sb600.h>
 
 /*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
 /* pm_base should be got from bar2 of rs690. Here I compact ACPI
  * registers into 32 bytes limit.
  * */
diff --git a/src/mainboard/sunw/ultra40/get_bus_conf.c b/src/mainboard/sunw/ultra40/get_bus_conf.c
index a74048b3ca..4ed57467b4 100644
--- a/src/mainboard/sunw/ultra40/get_bus_conf.c
+++ b/src/mainboard/sunw/ultra40/get_bus_conf.c
@@ -188,7 +188,7 @@ void get_bus_conf(void)
 
 	/* CK804b */
 
-	if (pci1234[2] & 0xf) {	//if the second cpu is installed
+	if (pci1234[2] & 0xf) {	//if the second CPU is installed
 		bus_ck804b_0 = (pci1234[2] >> 16) & 0xff;
 #if 0
 		dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x09, 0));
diff --git a/src/mainboard/sunw/ultra40m2/get_bus_conf.c b/src/mainboard/sunw/ultra40m2/get_bus_conf.c
index c70cbec87b..b57f957c60 100644
--- a/src/mainboard/sunw/ultra40m2/get_bus_conf.c
+++ b/src/mainboard/sunw/ultra40m2/get_bus_conf.c
@@ -79,7 +79,7 @@ static unsigned get_hcid(unsigned i)
 
 	// we may need more way to find out hcid: subsystem id? GPIO read ?
 
-	// we need use id for 1. bus num, 2. mptable, 3. acpi table
+	// we need use id for 1. bus num, 2. mptable, 3. ACPI table
 
 	return id;
 }
diff --git a/src/mainboard/sunw/ultra40m2/resourcemap.c b/src/mainboard/sunw/ultra40m2/resourcemap.c
index 5235b0d87e..30ce9ea661 100644
--- a/src/mainboard/sunw/ultra40m2/resourcemap.c
+++ b/src/mainboard/sunw/ultra40m2/resourcemap.c
@@ -265,8 +265,8 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000103, /* link 1 of cpu 0 --> Nvidia MCP55 Pro */
-//		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */
+//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000103, /* link 1 of CPU 0 --> Nvidia MCP55 Pro */
+//		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */
 		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
 
diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c
index 014c3b6e05..7a5ce93319 100644
--- a/src/mainboard/sunw/ultra40m2/romstage.c
+++ b/src/mainboard/sunw/ultra40m2/romstage.c
@@ -181,5 +181,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
-	post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+	post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
 }
diff --git a/src/mainboard/supermicro/h8dme/resourcemap.c b/src/mainboard/supermicro/h8dme/resourcemap.c
index 2c6fef019e..22c61f49d2 100644
--- a/src/mainboard/supermicro/h8dme/resourcemap.c
+++ b/src/mainboard/supermicro/h8dme/resourcemap.c
@@ -265,7 +265,7 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */
+		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */
 		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index b48ea46dc1..aeff991355 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -204,5 +204,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
-	post_cache_as_ram();	// bsp swtich stack to ram and copy sysinfo ram now
+	post_cache_as_ram();	// bsp swtich stack to RAM and copy sysinfo RAM now
 }
diff --git a/src/mainboard/supermicro/h8dmr/resourcemap.c b/src/mainboard/supermicro/h8dmr/resourcemap.c
index 2c6fef019e..22c61f49d2 100644
--- a/src/mainboard/supermicro/h8dmr/resourcemap.c
+++ b/src/mainboard/supermicro/h8dmr/resourcemap.c
@@ -265,7 +265,7 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */
+		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */
 		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index 96672e929b..eb7381724e 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -181,5 +181,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
-        post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+        post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
 }
diff --git a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c
index b71448a920..b35d3e549a 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c
@@ -268,7 +268,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the highest bus number in configuration region i
 		 */
 		// WARD CHANGED
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c
index 1a32abf209..bab438e6d4 100644
--- a/src/mainboard/supermicro/h8qgi/romstage.c
+++ b/src/mainboard/supermicro/h8qgi/romstage.c
@@ -103,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x42);
 
 	post_code(0x50);
-	printk(BIOS_DEBUG, "Disabling cache as ram ");
+	printk(BIOS_DEBUG, "Disabling cache as RAM ");
 	disable_cache_as_ram();
 	printk(BIOS_DEBUG, "done\n");
 
diff --git a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c
index b71448a920..b35d3e549a 100644
--- a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c
+++ b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c
@@ -268,7 +268,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the highest bus number in configuration region i
 		 */
 		// WARD CHANGED
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c
index 071f2477db..fecb91a691 100644
--- a/src/mainboard/supermicro/h8scm/romstage.c
+++ b/src/mainboard/supermicro/h8scm/romstage.c
@@ -97,7 +97,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x42);
 
 	post_code(0x50);
-	printk(BIOS_DEBUG, "Disabling cache as ram ");
+	printk(BIOS_DEBUG, "Disabling cache as RAM ");
 	disable_cache_as_ram();
 	printk(BIOS_DEBUG, "done\n");
 
diff --git a/src/mainboard/technexion/tim5690/fadt.c b/src/mainboard/technexion/tim5690/fadt.c
index 4afb0b9e4c..f9768b20bd 100644
--- a/src/mainboard/technexion/tim5690/fadt.c
+++ b/src/mainboard/technexion/tim5690/fadt.c
@@ -25,7 +25,7 @@
 #include "southbridge/amd/sb600/sb600.h"
 
 /*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
 /* pm_base should be got from bar2 of rs690. Here I compact ACPI
  * registers into 32 bytes limit.
  * */
diff --git a/src/mainboard/technexion/tim8690/fadt.c b/src/mainboard/technexion/tim8690/fadt.c
index 4afb0b9e4c..f9768b20bd 100644
--- a/src/mainboard/technexion/tim8690/fadt.c
+++ b/src/mainboard/technexion/tim8690/fadt.c
@@ -25,7 +25,7 @@
 #include "southbridge/amd/sb600/sb600.h"
 
 /*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
 /* pm_base should be got from bar2 of rs690. Here I compact ACPI
  * registers into 32 bytes limit.
  * */
diff --git a/src/mainboard/traverse/geos/irq_tables.c b/src/mainboard/traverse/geos/irq_tables.c
index 35d5fa6083..3e2e1d99a1 100644
--- a/src/mainboard/traverse/geos/irq_tables.c
+++ b/src/mainboard/traverse/geos/irq_tables.c
@@ -52,7 +52,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	{
 	 /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
 	 /* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
-	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* cpu */
+	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* CPU */
 	 {0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* eth0 */
 	 {0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* eth1 */
 	 {0x00, (0x0C << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x2, 0x0}, /* xilinx */
diff --git a/src/mainboard/tyan/s2912/resourcemap.c b/src/mainboard/tyan/s2912/resourcemap.c
index f0ae405737..9ac7ae4536 100644
--- a/src/mainboard/tyan/s2912/resourcemap.c
+++ b/src/mainboard/tyan/s2912/resourcemap.c
@@ -265,8 +265,8 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */
-//		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 	*/
+//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */
+//		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 	*/
 		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
 
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index 751cf71de0..c80e2d6061 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -184,5 +184,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
-	post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+	post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
 }
diff --git a/src/mainboard/tyan/s2912_fam10/resourcemap.c b/src/mainboard/tyan/s2912_fam10/resourcemap.c
index a78643a599..14e3c537f7 100644
--- a/src/mainboard/tyan/s2912_fam10/resourcemap.c
+++ b/src/mainboard/tyan/s2912_fam10/resourcemap.c
@@ -265,8 +265,8 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 	*/
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 	*/
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
 
diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c
index 13b4054a27..ea877b738f 100644
--- a/src/mainboard/tyan/s8226/romstage.c
+++ b/src/mainboard/tyan/s8226/romstage.c
@@ -106,7 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x42);
 
 	post_code(0x50);
-	printk(BIOS_DEBUG, "Disabling cache as ram ");
+	printk(BIOS_DEBUG, "Disabling cache as RAM ");
 	disable_cache_as_ram();
 	printk(BIOS_DEBUG, "done\n");
 
diff --git a/src/mainboard/winent/pl6064/irq_tables.c b/src/mainboard/winent/pl6064/irq_tables.c
index 4de63c48de..019e713854 100644
--- a/src/mainboard/winent/pl6064/irq_tables.c
+++ b/src/mainboard/winent/pl6064/irq_tables.c
@@ -53,7 +53,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	{
 	 /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
 	 /* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
-	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* cpu */
+	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* CPU */
 	 {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},	/* chipset */
 	 {0x00, (0x09 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* ethernet 0*/
 	 {0x00, (0x0A << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* ethernet 1*/