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authorFurquan Shaikh <furquan@chromium.org>2018-02-05 12:08:57 -0800
committerFurquan Shaikh <furquan@google.com>2018-02-07 04:29:53 +0000
commit9076b7bd077810cb219ef2a58e999fad2b3e0b93 (patch)
tree7c98d91895ba960ea8edcf06c3a463702f52b69e /src
parent278a5064b4a8e7c0a5742872a9d5b4464e22da00 (diff)
downloadcoreboot-9076b7bd077810cb219ef2a58e999fad2b3e0b93.tar.xz
mb/google/poppy/variants/nami: Change WiFi wake pin to GPP_E22
This change updates the WiFi device wake pin to GPP_E22 from WAKE# (to match the latest schematic changes). Since WiFi was the only device using WAKE# pin, DSX_EN_WAKE_PIN is removed from deep_sx_config as well. BUG=b:72697650 TEST=Verified: 1. Wake-on-wifi works. 2. Device is able to enter G3 without WAKE# pin causing unwanted wakes from deep S5. Change-Id: Ibde81f73cca322f9b8b45baf8ee18ae00521467d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23594 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/poppy/variants/nami/devicetree.cb4
-rw-r--r--src/mainboard/google/poppy/variants/nami/gpio.c4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index 348f7de3d0..55ecb26c11 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -5,7 +5,7 @@ chip soc/intel/skylake
register "deep_s3_enable_dc" = "1"
register "deep_s5_enable_ac" = "1"
register "deep_s5_enable_dc" = "1"
- register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"
+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"
# GPE configuration
# Note that GPE events called out in ASL code rely on this
@@ -291,7 +291,7 @@ chip soc/intel/skylake
device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 on
chip drivers/intel/wifi
- register "wake" = "GPE0_PCI_EXP"
+ register "wake" = "GPE0_DW2_22" # Wake pin = GPP_E22
device pci 00.0 on end
end
end # PCI Express Port 4
diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c
index dbee643e4d..e85d948b20 100644
--- a/src/mainboard/google/poppy/variants/nami/gpio.c
+++ b/src/mainboard/google/poppy/variants/nami/gpio.c
@@ -253,8 +253,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
/* E21 : DDPC_CTRLDATA ==> SOC_DP2_CTRL_DATA */
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
- /* E22 : DDPD_CTRLCLK ==> NC */
- PAD_CFG_NC(GPP_E22),
+ /* E22 : DDPD_CTRLCLK ==> WLAN_PCIE_WAKE# */
+ PAD_CFG_GPI_ACPI_SCI(GPP_E22, NONE, DEEP, INVERT),
/* E23 : DDPD_CTRLDATA ==> NC */
PAD_CFG_NC(GPP_E23),