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authorDuncan Laurie <dlaurie@chromium.org>2012-04-09 12:31:43 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-05-01 20:06:13 +0200
commit95be1d6f469a552657bc6a63ccdb27a7654f810f (patch)
tree2a41369a65a94e11c29395205582991ee1b5fbd8 /src
parent7b508ddecb25d60945f088914f739ee5b3c2c175 (diff)
downloadcoreboot-95be1d6f469a552657bc6a63ccdb27a7654f810f.tar.xz
Don't disable ACPI in the S3 resume path
The OS does not re-execute the APMC 'enable ACPI' SMI on resume so this has the potential to leave things in an unknown state. Change-Id: Iaf0fcb99f699e9e0ecacaab3f529026782a95151 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/971 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c15
1 files changed, 9 insertions, 6 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 9a3dc99b6a..dddab6a2a2 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -396,15 +396,18 @@ static void pch_lock_smm(struct device *dev)
u8 reg8;
#endif
+ if (acpi_slp_type != 3) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
- printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
- outb(0xe1, 0xb2); // Enable ACPI mode
- printk(BIOS_DEBUG, "done.\n");
+ printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
+ outb(0xe1, 0xb2); // Enable ACPI mode
+ printk(BIOS_DEBUG, "done.\n");
#else
- printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
- outb(0x1e, 0xb2); // Disable ACPI mode
- printk(BIOS_DEBUG, "done.\n");
+ printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
+ outb(0x1e, 0xb2); // Disable ACPI mode
+ printk(BIOS_DEBUG, "done.\n");
#endif
+ }
+
/* Don't allow evil boot loaders, kernels, or
* userspace applications to deceive us:
*/