mb/gigabyte/ga-h61m-s2pv: Add new mainboard

Tested with GRUB 2.02 as a payload, booting Arch Linux with
latest kernel. This code is based on the output of autoport
as well as existing ga-b75m-d3h and ga-b75m-d3v mainboards.

Working:
 - Serial port I/O
 - S3 suspend/resume (broken with SeaBIOS 1.11.1)
 - USB ports and headers
 - Gigabit Ethernet
 - Integrated graphics (libgfxinit)
 - PCIe x16 graphics
 - PCIe x1
 - SATA controller
 - Hardware Monitor
 - Fan Control (fancontrol on linux works well)
 - Native raminit (4+4GB, 4+2GB, 2+2GB, DDR3-1333)
 - Native graphics init with libgfxinit
 - flashrom, using the internal programmer. Tested with coreboot,
   as well as with the vendor firmware. Backup chip is untested.
 - NVRAM settings. Only `gfx_uma_size` and `debug_level` have been
   tested with values different from the default.

Untested:
 - VGA BIOS for integrated graphics init
 - DVI port. It can detect a "fake" display, that is, an
   EEPROM connected to the DVI port.
 - PS/2 ports
 - Audio: Only rear output (green) has been tested.
 - EHCI debug.
 - Parallel port
 - Non-Linux OSes
 - ACPI thermal zone and fan control (probably not working)

Not working:
 - SATA devices with Tianocore (payload issue)
 - PCIe to PCI bridge. It seems to be poorly supported on Linux,
   it lacks a public datasheet and vendor BIOS behaves in the
   same way: The bridge and the devices behind it appear, but
   drivers fail to find devices attached to the bridge.

Change-Id: I598a0b75093a0f1aef2ac615035d66786a8c22cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/25912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

19 files changed, 928 insertions, 0 deletions

diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig
new file mode 100644
index 0000000000..f53bc069eb
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig
@@ -0,0 +1,75 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+if BOARD_GIGABYTE_GA_H61M_S2PV
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select ARCH_X86
+	select BOARD_ROMSIZE_KB_4096
+	select CPU_INTEL_SOCKET_LGA1155
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select INTEL_INT15
+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
+	select SERIRQ_CONTINUOUS_MODE
+	select SOUTHBRIDGE_INTEL_BD82X6X
+	select USE_NATIVE_RAMINIT
+	select SUPERIO_ITE_IT8728F
+	select MAINBOARD_HAS_LIBGFXINIT
+	select HAVE_OPTION_TABLE
+	select HAVE_CMOS_DEFAULT
+
+config HAVE_IFD_BIN
+	bool
+	default n
+
+config HAVE_ME_BIN
+	bool
+	default n
+
+config MAINBOARD_DIR
+	string
+	default "gigabyte/ga-h61m-s2pv"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "GA-H61M-S2PV"
+
+config VGA_BIOS_FILE
+	string
+	default "pci8086,0102.rom"
+
+config VGA_BIOS_ID
+	string
+	default "8086,0102"
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+	hex
+	default 0x5001
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x1458
+
+config MAX_CPUS
+	int
+	default 8
+
+config USBDEBUG_HCD_INDEX # FIXME: check this
+	int
+	default 2
+
+endif # BOARD_GIGABYTE_GA_H61M_S2PV
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name
new file mode 100644
index 0000000000..04da3f01cf
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_GIGABYTE_GA_H61M_S2PV
+	bool "GA-H61M-S2PV"
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc b/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc
new file mode 100644
index 0000000000..ea035d3876
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc
@@ -0,0 +1,3 @@
+romstage-y += gpio.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/ec.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/ec.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/ec.asl
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/mainboard.asl
new file mode 100644
index 0000000000..34de86f976
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/mainboard.asl
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB)
+{
+	Device (PWRB)
+	{
+		Name (_HID, EisaId("PNP0C0C"))
+	}
+}
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/platform.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/platform.asl
new file mode 100644
index 0000000000..d8d33208f8
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/platform.asl
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	Return(Package(){0,0})
+}
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/superio.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/superio.asl
new file mode 100644
index 0000000000..78bf687938
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/superio.asl
@@ -0,0 +1,19 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+
+#define SIO_EC_ENABLE_PS2K       // Enable PS/2 Keyboard
+#define SIO_ENABLE_PS2M          // Enable PS/2 Mouse
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/thermal.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/thermal.asl
new file mode 100644
index 0000000000..c2bc80c84f
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/thermal.asl
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+	ThermalZone (THRM)
+	{
+		Name (_TC1, 0x02)
+		Name (_TC2, 0x03)
+
+		// Thermal zone polling frequency: 10 seconds
+		Name (_TZP, 100)
+
+		// Thermal sampling period for passive cooling: 10 seconds
+		Name (_TSP, 100)
+
+		// Convert from Degrees C to 1/10 Kelvin for ACPI
+		Method (CTOK, 1)
+		{
+			// 10th of Degrees C
+			Multiply (Arg0, 10, Local0)
+
+			// Convert to Kelvin
+			Add (Local0, 2732, Local0)
+
+			Return (Local0)
+		}
+
+		// Threshold for OS to shutdown
+		Method (_CRT, 0, Serialized)
+		{
+			Return (CTOK (\TCRT))
+		}
+
+		// Threshold for passive cooling
+		Method (_PSV, 0, Serialized)
+		{
+			Return (CTOK (\TPSV))
+		}
+
+		// Processors used for passive cooling
+		Method (_PSL, 0, Serialized)
+		{
+			Return (\PPKG ())
+		}
+	}
+}
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi_tables.c b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi_tables.c
new file mode 100644
index 0000000000..5eb07796c6
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi_tables.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	/* Disable USB ports in S3 by default */
+	gnvs->s3u0 = 0;
+	gnvs->s3u1 = 0;
+
+	/* Disable USB ports in S5 by default */
+	gnvs->s5u0 = 0;
+	gnvs->s5u1 = 0;
+}
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/board_info.txt b/src/mainboard/gigabyte/ga-h61m-s2pv/board_info.txt
new file mode 100644
index 0000000000..ef0d22c07e
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/board_info.txt
@@ -0,0 +1,6 @@
+Category: desktop
+Board URL: https://www.gigabyte.com/Motherboard/GA-H61M-S2PV-rev-23#ov
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/cmos.default b/src/mainboard/gigabyte/ga-h61m-s2pv/cmos.default
new file mode 100644
index 0000000000..6f3cec735e
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/cmos.default
@@ -0,0 +1,6 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Enable
+nmi=Enable
+sata_mode=AHCI
+gfx_uma_size=32M
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/cmos.layout b/src/mainboard/gigabyte/ga-h61m-s2pv/cmos.layout
new file mode 100644
index 0000000000..8bafc6f9c0
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/cmos.layout
@@ -0,0 +1,112 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2014 Vladimir Serbinenko
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+388          4       h       0        reboot_counter
+#390          2       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+#392          3       r       0        unused
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+409          2       e       7        power_on_after_fail
+
+#411       10       r       0        unused
+421         1       e       9        sata_mode
+#422	    2	    r	    0	     unused
+
+# coreboot config options: cpu
+#425        7       r       0        unused
+
+# coreboot config options: northbridge
+432         3        e      11        gfx_uma_size
+#435        549       r       0        unused
+
+# SandyBridge MRC Scrambler Seed values
+896         32        r       0        mrc_scrambler_seed
+928         32        r       0        mrc_scrambler_seed_s3
+960         16        r       0        mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+4     0     Fallback
+4     1     Normal
+6     0     Emergency
+6     1     Alert
+6     2     Critical
+6     3     Error
+6     4     Warning
+6     5     Notice
+6     6     Info
+6     7     Debug
+6     8     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+9     0     AHCI
+9     1     IDE
+11    0     32M
+11    1     64M
+11    2	    96M
+11    3	    128M
+11    4	    160M
+11    5	    192M
+11    6	    224M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb
new file mode 100644
index 0000000000..3ba8558a09
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb
@@ -0,0 +1,117 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+chip northbridge/intel/sandybridge
+	register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
+	register "gfx.link_frequency_270_mhz" = "0"
+	register "gfx.ndid" = "3"
+	register "gfx.use_spread_spectrum_clock" = "0"
+	register "gpu_dp_b_hotplug" = "4"
+	register "gpu_dp_c_hotplug" = "4"
+	register "gpu_dp_d_hotplug" = "4"
+	register "gpu_panel_port_select" = "0"
+	device cpu_cluster 0x0 on
+		chip cpu/intel/socket_LGA1155
+			device lapic 0x0 on
+			end
+		end
+		chip cpu/intel/model_206ax
+			register "c1_acpower" = "1"
+			register "c1_battery" = "1"
+			register "c2_acpower" = "3"
+			register "c2_battery" = "3"
+			register "c3_acpower" = "5"
+			register "c3_battery" = "5"
+			device lapic 0xacac off
+			end
+		end
+	end
+	register "pci_mmio_size" = "2048"
+	device domain 0x0 on
+		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+			register "c2_latency" = "0x0065"
+			register "docking_supported" = "0"
+			register "gen1_dec" = "0x003c0a01"
+			register "p_cnt_throttling_supported" = "0"
+			register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
+			register "pcie_port_coalesce" = "1"
+			register "sata_interface_speed_support" = "0x3"
+			register "sata_port_map" = "0x33"
+			register "spi_lvscc" = "0x2005"
+			register "spi_uvscc" = "0x2005"
+			device pci 16.0 on  end	# Management Engine Interface 1
+			device pci 16.1 off end	# Management Engine Interface 2
+			device pci 16.2 off end	# Management Engine IDE-R
+			device pci 16.3 off end	# Management Engine KT
+			device pci 19.0 off end	# Intel Gigabit Ethernet
+			device pci 1a.0 on  end	# USB2 EHCI #2
+			device pci 1b.0 on  end	# High Definition Audio Audio controller
+			device pci 1c.0 on  end	# PCIe x1 Port (PCIEX1)
+			device pci 1c.1 off end	# Unused PCIe Port
+			device pci 1c.2 off end	# Unused PCIe Port
+			device pci 1c.3 off end	# Unused PCIe Port
+			device pci 1c.4 on  end	# Realtek RTL8111F Ethernet Controller
+			device pci 1c.5 on  end	# ITE IT8892F PCIe to PCI bridge
+			device pci 1c.6 off end	# Unused PCIe Port
+			device pci 1c.7 off end	# Unused PCIe Port
+			device pci 1d.0 on  end	# USB2 EHCI #1
+			device pci 1e.0 on  end	# PCI bridge
+			device pci 1f.0 on	# LPC bridge
+				chip superio/ite/it8728f
+					device pnp 2e.0 off end		# Floppy, not routed.
+					device pnp 2e.1 on		# COM1
+						io 0x60 = 0x03f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.2 off end		# COM2, not routed.
+					device pnp 2e.3 on		# Parallel port
+						io 0x60 = 0x0378
+						irq 0x70 = 7
+						drq 0x74 = 4
+					end
+					device pnp 2e.4 on 		# Environment Controller
+						io 0x60 = 0x0a30
+						irq 0x70 = 9
+						io 0x62 = 0x0a20
+					end
+					device pnp 2e.5 on		# Keyboard
+						io 0x60 = 0x60
+						irq 0x70 = 1
+						io 0x62 = 0x64
+					end
+					device pnp 2e.6 on		# Mouse
+						irq 0x70 = 12
+					end
+					device pnp 2e.7 off		# GPIO
+						io 0x25 = 0x40
+						io 0x27 = 0x10
+						io 0x2c = 0x80
+						io 0x62 = 0x0a00
+						io 0xcb = 0x00
+						io 0xf1 = 0x40
+					end
+					device pnp 2e.a off end		# CIR, not routed.
+				end
+			end
+			device pci 1f.2 on  end	# SATA Controller 1
+			device pci 1f.3 on  end	# SMBus
+			device pci 1f.5 off end	# SATA Controller 2
+			device pci 1f.6 off end	# Thermal
+		end
+		device pci 00.0 on end	# Host bridge
+		device pci 01.0 on end	# PCIe Bridge for discrete graphics (PCIEX16)
+		device pci 02.0 on end	# Internal graphics VGA controller
+	end
+end
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl
new file mode 100644
index 0000000000..d5719cc58c
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x03,		// DSDT revision: ACPI v3.0
+	"COREv4",	// OEM id
+	"COREBOOT",	// OEM table id
+	0x20141018	// OEM revision
+)
+{
+	// Some generic macros
+	#include "acpi/mainboard.asl"
+	#include "acpi/platform.asl"
+	#include "acpi/superio.asl"
+	#include "acpi/thermal.asl"
+	#include <cpu/intel/model_206ax/acpi/cpu.asl>
+	#include <southbridge/intel/bd82x6x/acpi/platform.asl>
+
+	/* global NVS and variables.  */
+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+	#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
+		}
+	}
+}
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/gma-mainboard.ads b/src/mainboard/gigabyte/ga-h61m-s2pv/gma-mainboard.ads
new file mode 100644
index 0000000000..2083ff0f1f
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/gma-mainboard.ads
@@ -0,0 +1,29 @@
+--
+-- This file is part of the coreboot project.
+--
+-- Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; version 2 of the License.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (HDMI1,
+      Analog,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/gpio.c b/src/mainboard/gigabyte/ga-h61m-s2pv/gpio.c
new file mode 100644
index 0000000000..f7de3bd9c2
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/gpio.c
@@ -0,0 +1,202 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_GPIO,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_NATIVE,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_INPUT,
+	.gpio3 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio5 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_OUTPUT,
+	.gpio12 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_OUTPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_INPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio8 = GPIO_LEVEL_HIGH,
+	.gpio12 = GPIO_LEVEL_HIGH,
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio24 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_NATIVE,
+	.gpio46 = GPIO_MODE_NATIVE,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_NATIVE,
+	.gpio51 = GPIO_MODE_NATIVE,
+	.gpio52 = GPIO_MODE_NATIVE,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_NATIVE,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_NATIVE,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_OUTPUT,
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio35 = GPIO_DIR_OUTPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio32 = GPIO_LEVEL_HIGH,
+	.gpio33 = GPIO_LEVEL_HIGH,
+	.gpio35 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_NATIVE,
+	.gpio71 = GPIO_MODE_NATIVE,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-s2pv/hda_verb.c
new file mode 100644
index 0000000000..15a2b0159c
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/hda_verb.c
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0887, /* Codec Vendor / Device ID: Realtek */
+	0x1458a002, /* Subsystem ID */
+
+	0x0000000f, /* Number of 4 dword sets */
+	/* NID 0x01: Subsystem ID.  */
+	AZALIA_SUBVENDOR(0x2, 0x1458a002),
+
+	/* NID 0x11.  */
+	AZALIA_PIN_CFG(0x2, 0x11, 0x411111f0),
+
+	/* NID 0x12.  */
+	AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0),
+
+	/* NID 0x14.  */
+	AZALIA_PIN_CFG(0x2, 0x14, 0x01014410),
+
+	/* NID 0x15.  */
+	AZALIA_PIN_CFG(0x2, 0x15, 0x411111f0),
+
+	/* NID 0x16.  */
+	AZALIA_PIN_CFG(0x2, 0x16, 0x411111f0),
+
+	/* NID 0x17.  */
+	AZALIA_PIN_CFG(0x2, 0x17, 0x411111f0),
+
+	/* NID 0x18.  */
+	AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c50),
+
+	/* NID 0x19.  */
+	AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c60),
+
+	/* NID 0x1a.  */
+	AZALIA_PIN_CFG(0x2, 0x1a, 0x0181345f),
+
+	/* NID 0x1b.  */
+	AZALIA_PIN_CFG(0x2, 0x1b, 0x02214c20),
+
+	/* NID 0x1c.  */
+	AZALIA_PIN_CFG(0x2, 0x1c, 0x411111f0),
+
+	/* NID 0x1d.  */
+	AZALIA_PIN_CFG(0x2, 0x1d, 0x4004c601),
+
+	/* NID 0x1e.  */
+	AZALIA_PIN_CFG(0x2, 0x1e, 0x411111f0),
+
+	/* NID 0x1f.  */
+	AZALIA_PIN_CFG(0x2, 0x1f, 0x411111f0),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/mainboard.c b/src/mainboard/gigabyte/ga-h61m-s2pv/mainboard.c
new file mode 100644
index 0000000000..b8a659bfa3
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/mainboard.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+static void mainboard_enable(struct device *dev)
+{
+	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
+					GMA_INT15_PANEL_FIT_DEFAULT,
+					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
new file mode 100644
index 0000000000..3e63721bd3
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8728f/it8728f.h>
+
+#define SUPERIO_GPIO PNP_DEV(0x2e, IT8728F_GPIO)
+#define SERIAL_DEV PNP_DEV(0x2e, 0x01)
+
+void pch_enable_lpc(void)
+{
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN |
+			CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
+
+	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
+}
+
+void mainboard_rcba_config(void)
+{
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1, 0, 0 },
+	{ 1, 0, 0 },
+	{ 1, 0, 1 },
+	{ 1, 0, 1 },
+	{ 1, 0, 2 },
+	{ 1, 0, 2 },
+	{ 1, 0, 3 },
+	{ 1, 0, 3 },
+	{ 1, 0, 4 },
+	{ 1, 0, 4 },
+	{ 1, 0, 6 },
+	{ 1, 0, 5 },
+	{ 1, 0, 5 },
+	{ 1, 0, 6 },
+};
+
+void mainboard_early_init(int s3resume)
+{
+}
+
+void mainboard_config_superio(void)
+{
+	/* Enable serial port and flip some magic bits */
+
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+	ite_reg_write(SUPERIO_GPIO, 0xEF, 0x7E); // magic
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	read_spd(&spd[0], 0x50, id_only);
+	read_spd(&spd[2], 0x52, id_only);
+}