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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-03 23:18:01 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-08 04:51:32 +0000
commit9970b61ad3049d87650cd7b4eb5f47d667098186 (patch)
tree912ee2624ebd4d9c68ab62cbde170c1e5d114b0f /src
parent0a4457ff44b10f22b711f64e88888c757fbedf32 (diff)
downloadcoreboot-9970b61ad3049d87650cd7b4eb5f47d667098186.tar.xz
arch/x86: Move TSEG_STAGE_CACHE implementation
This is declared weak so that platforms that do not have smm_subregion() can provide their own implementation. Change-Id: Ide815b45cbc21a295b8e58434644e82920e84e31 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/cpu/x86/smm/Makefile.inc4
-rw-r--r--src/cpu/x86/smm/stage_cache.c (renamed from src/drivers/intel/fsp1_1/stage_cache.c)11
-rw-r--r--src/drivers/intel/fsp1_1/Makefile.inc3
-rw-r--r--src/soc/amd/picasso/ramtop.c10
-rw-r--r--src/soc/amd/stoneyridge/ramtop.c10
-rw-r--r--src/soc/intel/common/block/smm/smm.c12
6 files changed, 12 insertions, 38 deletions
diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc
index 5c7aab3ffc..fe149f140f 100644
--- a/src/cpu/x86/smm/Makefile.inc
+++ b/src/cpu/x86/smm/Makefile.inc
@@ -42,6 +42,10 @@ endif
ifeq ($(CONFIG_SMM_TSEG),y)
+ramstage-y += stage_cache.c
+romstage-y += stage_cache.c
+postcar-y += stage_cache.c
+
smmstub-y += smm_stub.S
smm-y += smm_module_handler.c
diff --git a/src/drivers/intel/fsp1_1/stage_cache.c b/src/cpu/x86/smm/stage_cache.c
index ab0c1c0126..7806290d5c 100644
--- a/src/drivers/intel/fsp1_1/stage_cache.c
+++ b/src/cpu/x86/smm/stage_cache.c
@@ -1,8 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corp.
+ * Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,8 +16,14 @@
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <stage_cache.h>
+#include <types.h>
-void stage_cache_external_region(void **base, size_t *size)
+int __weak smm_subregion(int sub, void **base, size_t *size)
+{
+ return -1;
+}
+
+void __weak stage_cache_external_region(void **base, size_t *size)
{
if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc
index 10877b9482..1372e98565 100644
--- a/src/drivers/intel/fsp1_1/Makefile.inc
+++ b/src/drivers/intel/fsp1_1/Makefile.inc
@@ -29,7 +29,6 @@ romstage-y += fsp_util.c
romstage-y += hob.c
romstage-y += raminit.c
romstage-y += romstage.c
-romstage-y += stage_cache.c
romstage-$(CONFIG_MMA) += mma_core.c
ramstage-$(CONFIG_RUN_FSP_GOP) += fsp_gop.c
@@ -37,13 +36,11 @@ ramstage-y += fsp_relocate.c
ramstage-y += fsp_util.c
ramstage-y += hob.c
ramstage-y += ramstage.c
-ramstage-y += stage_cache.c
ramstage-$(CONFIG_INTEL_GMA_ADD_VBT) += vbt.c
ramstage-$(CONFIG_MMA) += mma_core.c
CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include
-postcar-y += stage_cache.c
ifneq ($(CONFIG_SKIP_FSP_CAR),y)
postcar-y += temp_ram_exit.c
postcar-y += exit_car.S
diff --git a/src/soc/amd/picasso/ramtop.c b/src/soc/amd/picasso/ramtop.c
index 4ff4252c76..f0051e4bfe 100644
--- a/src/soc/amd/picasso/ramtop.c
+++ b/src/soc/amd/picasso/ramtop.c
@@ -23,7 +23,6 @@
#include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h>
#include <cbmem.h>
-#include <stage_cache.h>
#include <arch/bert_storage.h>
#include <soc/northbridge.h>
#include <soc/iomap.h>
@@ -82,15 +81,6 @@ static size_t smm_region_size(void)
return CONFIG_SMM_TSEG_SIZE;
}
-void stage_cache_external_region(void **base, size_t *size)
-{
- if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
- printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
- *base = NULL;
- *size = 0;
- }
-}
-
void smm_region(void **start, size_t *size)
{
*start = (void *)smm_region_start();
diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c
index 4ff4252c76..f0051e4bfe 100644
--- a/src/soc/amd/stoneyridge/ramtop.c
+++ b/src/soc/amd/stoneyridge/ramtop.c
@@ -23,7 +23,6 @@
#include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h>
#include <cbmem.h>
-#include <stage_cache.h>
#include <arch/bert_storage.h>
#include <soc/northbridge.h>
#include <soc/iomap.h>
@@ -82,15 +81,6 @@ static size_t smm_region_size(void)
return CONFIG_SMM_TSEG_SIZE;
}
-void stage_cache_external_region(void **base, size_t *size)
-{
- if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
- printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
- *base = NULL;
- *size = 0;
- }
-}
-
void smm_region(void **start, size_t *size)
{
*start = (void *)smm_region_start();
diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c
index 489462dfa7..12c057b25a 100644
--- a/src/soc/intel/common/block/smm/smm.c
+++ b/src/soc/intel/common/block/smm/smm.c
@@ -22,18 +22,6 @@
#include <intelblocks/smm.h>
#include <intelblocks/systemagent.h>
#include <soc/pm.h>
-#include <stage_cache.h>
-
-#if !CONFIG(PLATFORM_USES_FSP1_1)
-void stage_cache_external_region(void **base, size_t *size)
-{
- if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
- printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
- *base = NULL;
- *size = 0;
- }
-}
-#endif
void smm_southbridge_clear_state(void)
{