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authorPaul Menzel <paulepanter@users.sourceforge.net>2014-06-05 08:50:17 +0200
committerPatrick Georgi <pgeorgi@google.com>2014-12-19 21:14:52 +0100
commit9d3e131461e36229a3a4bbcd16a430a62be37e10 (patch)
tree4712b676b48087751f077cef88e037d48f7c9ac4 /src
parentccf53af8a99aba3273fc7d515480c5b6826f4287 (diff)
downloadcoreboot-9d3e131461e36229a3a4bbcd16a430a62be37e10.tar.xz
intel/i945: Use define for `BSM`
Change-Id: Ia58d8b410a145f27f0b267c115714580c366e063 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5929 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/i945/early_init.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index b12ad3a63e..0b2acd70b7 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -943,7 +943,7 @@ void i945_late_initialization(int s3resume)
{
/* This will not work if TSEG is in place! */
- u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), 0x5c);
+ u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM);
printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
ram_check(0x00000000, 0x000a0000);