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authorVadim Bendebury <vbendeb@chromium.org>2016-05-22 16:09:54 -0700
committerMartin Roth <martinroth@google.com>2016-06-08 23:21:55 +0200
commit9ed93cb5d50f94f9c43db2eb29764cd6302b4bb0 (patch)
tree0dc76c952e9ed6269d28bf1ead9666ee6d4f2534 /src
parent221fdd8cce708f192a457f39a703e9a968b2f847 (diff)
downloadcoreboot-9ed93cb5d50f94f9c43db2eb29764cd6302b4bb0.tar.xz
gru: kevin: configure board GPIOs
Set board GPIOs as required and add their description into the appropriate section of the coreboot table, to make them available to depthcharge. BRANCH=none BUG=chrome-os-partner:51537 TEST=with the rest of the patches applied it is possible to use keyboard on Gru, which indicates that the EC interrupt GPIO is properly configured. The rest of the pins will be verified later. Change-Id: I5818bfe855f4e7faa2114484a9b7b44c7d469727 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: e02a05f Original-Change-Id: I82be76bbd3211179e696526a34cc842cb1987e69 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/346631 Reviewed-on: https://review.coreboot.org/15031 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/gru/bootblock.c4
-rw-r--r--src/mainboard/google/gru/chromeos.c24
-rw-r--r--src/soc/rockchip/rk3399/Makefile.inc2
3 files changed, 25 insertions, 5 deletions
diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c
index 1166d8a842..a048188e0a 100644
--- a/src/mainboard/google/gru/bootblock.c
+++ b/src/mainboard/google/gru/bootblock.c
@@ -21,6 +21,8 @@
#include <soc/spi.h>
#include <console/console.h>
+#include "board.h"
+
void bootblock_mainboard_early_init(void)
{
/* Let gpio2ab io domains works at 1.8V.
@@ -62,4 +64,6 @@ void bootblock_mainboard_init(void)
write32(&rk3399_pmugrf->spi1_csclktx, IOMUX_SPI1_CSCLKTX);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
+
+ setup_chromeos_gpios();
}
diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c
index da57d861c6..4265f8d9c1 100644
--- a/src/mainboard/google/gru/chromeos.c
+++ b/src/mainboard/google/gru/chromeos.c
@@ -15,15 +15,22 @@
*/
#include <boot/coreboot_tables.h>
+#include <gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
+#include "board.h"
+
void fill_lb_gpios(struct lb_gpios *gpios)
{
-}
+ struct lb_gpio chromeos_gpios[] = {
+ {GPIO_WP.raw, ACTIVE_LOW, gpio_get(GPIO_WP), "write protect"},
+ {GPIO_BACKLIGHT.raw, ACTIVE_HIGH, -1, "backlight"},
+ {GPIO_EC_IN_RW.raw, ACTIVE_HIGH, -1, "EC in RW"},
+ {GPIO_EC_IRQ.raw, ACTIVE_LOW, -1, "EC interrupt"},
+ {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"},
+ };
-int get_developer_mode_switch(void)
-{
- return 0;
+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
int get_recovery_mode_switch(void)
@@ -33,5 +40,12 @@ int get_recovery_mode_switch(void)
int get_write_protect_state(void)
{
- return 0;
+ return !gpio_get(GPIO_WP);
+}
+
+void setup_chromeos_gpios(void)
+{
+ gpio_input(GPIO_WP);
+ gpio_input_pullup(GPIO_EC_IN_RW);
+ gpio_input_pullup(GPIO_EC_IRQ);
}
diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc
index 8abafe362b..77958d577f 100644
--- a/src/soc/rockchip/rk3399/Makefile.inc
+++ b/src/soc/rockchip/rk3399/Makefile.inc
@@ -47,6 +47,8 @@ romstage-y += ../common/pwm.c
romstage-y += timer.c
romstage-y += romstage.c
romstage-y += tsadc.c
+romstage-y += gpio.c
+romstage-y += ../common/gpio.c
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