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authorJonathan Kollasch <jakllsch@kollasch.net>2010-10-19 13:39:38 +0000
committerJonathan A. Kollasch <jakllsch@kollasch.net>2010-10-19 13:39:38 +0000
commit9fe50695841aa44713f5ee0486ca25f7d39b724e (patch)
tree1d0cb3eed0f5e6f9ba2d8e14ce4f753b4f99da6b /src
parentd208c1aa2cfa2dd7da58c1f9d290310a2e10fb4a (diff)
downloadcoreboot-9fe50695841aa44713f5ee0486ca25f7d39b724e.tar.xz
Correct spelling of "spacing" (in comments).
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/i855/raminit.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c
index 604a5e1f59..539d161640 100644
--- a/src/northbridge/intel/i855/raminit.c
+++ b/src/northbridge/intel/i855/raminit.c
@@ -755,7 +755,7 @@ static void spd_set_dram_timing(const struct mem_controller *ctrl, uint8_t dimm_
*/
/*
- * Back to Back Read-Write command spaceing (DDR, different Rows/Bank)
+ * Back to Back Read-Write command spacing (DDR, different Rows/Bank)
*/
/* Set to a 3 clock back to back read to write turn around.
* 2 is a good delay if the CAS latency is 2.0 */
@@ -766,7 +766,7 @@ static void spd_set_dram_timing(const struct mem_controller *ctrl, uint8_t dimm_
dram_timing |= (1 << 28); // 3 clocks
/*
- * Back to Back Read-Write command spaceing (DDR, same or different Rows/Bank)
+ * Back to Back Read-Write command spacing (DDR, same or different Rows/Bank)
*/
dram_timing &= ~(3 << 26);
if (current_cas_latency == DRT_CAS_2_0)