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authorIdwer Vollering <vidwer@gmail.com>2014-03-11 15:43:35 +0000
committerPatrick Georgi <patrick@georgi-clan.de>2014-04-09 14:04:01 +0200
commita09dad0c77ff0365210f784b10d0516338a949b7 (patch)
treec33e6162654ac8b987525dc573be42c76a7091c1 /src
parent1a25c9cdfd3fd391328133ba94c63ecd1083e4f8 (diff)
downloadcoreboot-a09dad0c77ff0365210f784b10d0516338a949b7.tar.xz
asus/f2a85-m: conditionally show POST codes
Change-Id: I61e55601676c0825815d6520a874ccade8942379 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/5362 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/asus/f2a85-m/romstage.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index bc7546c121..ee9983d88f 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -67,6 +67,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 val;
u8 byte;
device_t dev;
+
+#if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)
+ hudson_pci_port80();
+#endif
+#if IS_ENABLED(CONFIG_POST_DEVICE_LPC)
+ hudson_lpc_port80();
+#endif
+
#if CONFIG_HAVE_ACPI_RESUME
void *resume_backup_memory;
#endif