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authorElyes HAOUAS <ehaouas@noos.fr>2020-04-29 09:32:22 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-06-03 12:20:33 +0000
commita1c767a19b0f617b95306bea4f6cbbd1f9907a6e (patch)
tree3de431e7c33c3442ff28b85cd2b1a3b3af7dd7a1 /src
parentd8717197ae50dc9f68fbbde2f331d19b1d737351 (diff)
downloadcoreboot-a1c767a19b0f617b95306bea4f6cbbd1f9907a6e.tar.xz
soc/tigerlake: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I1731313798a4aadcbc17808bfe02b50bf8bd41db Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/tigerlake/bootblock/pch.c11
1 files changed, 5 insertions, 6 deletions
diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
index e9b11767ae..9fc5ce167b 100644
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -50,22 +50,21 @@
static void soc_config_pwrmbase(void)
{
uint32_t reg32;
+ uint16_t reg16;
/*
* Assign Resources to PWRMBASE
* Clear BIT 1-2 Command Register
*/
- reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
- reg32 &= ~(PCI_COMMAND_MEMORY);
- pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
+ reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND);
+ reg16 &= ~(PCI_COMMAND_MEMORY);
+ pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16);
/* Program PWRM Base */
pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
/* Enable Bus Master and MMIO Space */
- reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MEMORY;
- pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
+ pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY);
/* Enable PWRM in PMC */
reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL));