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authorDuncan Laurie <dlaurie@chromium.org>2015-09-08 16:12:44 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-09-17 14:23:40 +0000
commita1c8b34d7b1b3a8df5b86faab79010c06b037445 (patch)
treea3ef38b194fe7094ee4ee7e7dd9ab6a440115b06 /src
parent47a0b8494b59cf292dcc3372a01ee597b6de3923 (diff)
downloadcoreboot-a1c8b34d7b1b3a8df5b86faab79010c06b037445.tar.xz
skylake: Use common ACPI _SWS code
Enable and use the common code for filling out the NVS data used by the _SWS methods. Add a function to provide the wake source data. With Deep S3 enabled skylake does not retain the contents of the PM1_EN register so instead just select the wake related events in PM1_STS. BUG=chrome-os-partner:40635 BRANCH=none TEST=tested on glados by checking for valid _SWS string in /sys/firmware/log after suspend/resume. Wake sources that were tested are RTC, power button, keypress, trackpad, and wifi. Change-Id: I93a4f740f2e2ef1c34e948db1d8e273332296921 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cb4d4705b87ef7169f1979009c34a58de93c4ef0 Original-Change-Id: Ib6b4df09ea3090894f09290d00dcdc5aebc3eabb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298169 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11648 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/skylake/Kconfig1
-rw-r--r--src/soc/intel/skylake/acpi.c21
-rw-r--r--src/soc/intel/skylake/acpi/platform.asl21
3 files changed, 25 insertions, 18 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 07c1d4140e..1ccde4ab02 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -37,6 +37,7 @@ config CPU_SPECIFIC_OPTIONS
select RELOCATABLE_MODULES
select RELOCATABLE_RAMSTAGE
select SOC_INTEL_COMMON
+ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_FSP_RAM_INIT
select SOC_INTEL_COMMON_FSP_ROMSTAGE
select SOC_INTEL_COMMON_RESET
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 5eec7c63dc..471fd17981 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -37,6 +37,7 @@
#include <cpu/intel/turbo.h>
#include <ec/google/chromeec/ec.h>
#include <vendorcode/google/chromeos/gnvs.h>
+#include <soc/intel/common/acpi.h>
#include <soc/acpi.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
@@ -604,6 +605,26 @@ void southcluster_inject_dsdt(device_t device)
}
}
+/* Save wake source information for calculating ACPI _SWS values */
+int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
+{
+ struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
+ static uint32_t gpe0_sts[GPE0_REG_MAX];
+ uint32_t pm1_en;
+ int i;
+
+ /* PM1_EN state is lost in Deep S3 so enable basic wake events */
+ pm1_en = ps->pm1_en | PCIEXPWAK_STS | RTC_STS | PWRBTN_STS | BM_STS;
+ *pm1 = ps->pm1_sts & pm1_en;
+
+ /* Mask off GPE0 status bits that are not enabled */
+ *gpe0 = &gpe0_sts[0];
+ for (i = 0; i < GPE0_REG_MAX; i++)
+ gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i];
+
+ return GPE0_REG_MAX;
+}
+
__attribute__((weak)) void acpi_mainboard_gnvs(global_nvs_t *gnvs)
{
}
diff --git a/src/soc/intel/skylake/acpi/platform.asl b/src/soc/intel/skylake/acpi/platform.asl
index f0ed4e0816..24df241edf 100644
--- a/src/soc/intel/skylake/acpi/platform.asl
+++ b/src/soc/intel/skylake/acpi/platform.asl
@@ -19,6 +19,9 @@
* Foundation, Inc.
*/
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+
/* The APM port can be used for generating software SMIs */
OperationRegion (APMP, SystemIO, 0xb2, 2)
@@ -83,21 +86,3 @@ Method (_WAK, 1)
{
Return (Package (){ 0, 0 })
}
-
-Scope (\_SB)
-{
- Method (_SWS)
- {
- /* Index into PM1 for device that caused wake */
- Return (\PM1I)
- }
-}
-
-Scope (\_GPE)
-{
- Method (_SWS)
- {
- /* Index into GPE for device that caused wake */
- Return (\GPEI)
- }
-}