summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorBarnali Sarkar <barnali.sarkar@intel.com>2015-12-18 15:44:23 +0530
committerPatrick Georgi <pgeorgi@google.com>2016-01-18 12:28:07 +0100
commita67526e61dcd4daf8311855a4b54eae7d63359a9 (patch)
treeb5a5414c4a3b7ea4fcf148b01519204789f2bb22 /src
parentc019cec4c0a585069ec144c6c7b801377f3506d3 (diff)
downloadcoreboot-a67526e61dcd4daf8311855a4b54eae7d63359a9.tar.xz
google/glados: Enable FspSkipMpInit token
MP init is already handled in coreboot, but it is also part of FSP. FSP has a implemented a provision to allow FSP to skip MP init and let coreboot handle it. BRANCH=none BUG=chrome-os-partner:44805 TEST=none CQ-DEPEND=CL:319353 Change-Id: I81c54582a3c980ecdcf329347bcd5982802d681c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e60ee81acaeb1062a31a3e78ed2ba4ccfe816ec5 Original-Change-Id: I71dd07559dffb7886e489274ffc8e71686ca730f Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319370 Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com> Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12994 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/glados/devicetree.cb1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index ccca4b3fad..62d2553aa8 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -43,6 +43,7 @@ chip soc/intel/skylake
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
+ register "FspSkipMpInit" = "1"
# VR Settings Configuration for 5 Domains
#+----------------+-------+-------+-------------+-------------+-------+