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authorGreg Watson <jarrah@users.sourceforge.net>2004-06-05 14:54:46 +0000
committerGreg Watson <jarrah@users.sourceforge.net>2004-06-05 14:54:46 +0000
commitab8ff84402e97d544b519ec17a2ee184651b8af6 (patch)
treea5e3d276108fbd280b9cd584412c5c9130b0c175 /src
parent8ce104f487a8248be143b4436b7a4abc3969bb6f (diff)
downloadcoreboot-ab8ff84402e97d544b519ec17a2ee184651b8af6.tar.xz
Add extra phase before memory init.
Rename sdram_init to memory_init NOTE: need to test sandpoint and ep boards! git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1603 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/arch/ppc/init/ppc_main.c13
-rw-r--r--src/cpu/ppc/ppc4xx/sdram.c2
-rw-r--r--src/mainboard/embeddedplanet/ep405pc/init.c5
-rw-r--r--src/mainboard/motorola/sandpoint/init.c13
-rw-r--r--src/mainboard/totalimpact/briq/init.c7
-rw-r--r--src/northbridge/ibm/cpc710/cpc710.c12
-rw-r--r--src/northbridge/motorola/mpc107/mpc107.c2
7 files changed, 39 insertions, 15 deletions
diff --git a/src/arch/ppc/init/ppc_main.c b/src/arch/ppc/init/ppc_main.c
index f7405fad33..4dd4487ae8 100644
--- a/src/arch/ppc/init/ppc_main.c
+++ b/src/arch/ppc/init/ppc_main.c
@@ -28,9 +28,20 @@ void ppc_main(void)
unsigned *from;
unsigned *to;
+ /*
+ * very early board initialization
+ */
board_init();
- sdram_init();
+ /*
+ * turn on memory
+ */
+ memory_init();
+
+ /*
+ * final initialization before jumping to payload
+ */
+ board_init2();
/*
* Flush cache now that memory is enabled.
diff --git a/src/cpu/ppc/ppc4xx/sdram.c b/src/cpu/ppc/ppc4xx/sdram.c
index 73cdcc364b..b8376caec5 100644
--- a/src/cpu/ppc/ppc4xx/sdram.c
+++ b/src/cpu/ppc/ppc4xx/sdram.c
@@ -60,7 +60,7 @@
/*-----------------------------------------------------------------------
*/
-void sdram_init(void)
+void memory_init(void)
{
#if 0
unsigned long speed;
diff --git a/src/mainboard/embeddedplanet/ep405pc/init.c b/src/mainboard/embeddedplanet/ep405pc/init.c
index 3f567a5c17..2359585e44 100644
--- a/src/mainboard/embeddedplanet/ep405pc/init.c
+++ b/src/mainboard/embeddedplanet/ep405pc/init.c
@@ -107,3 +107,8 @@ board_init(void)
udelay(100000);
out_8((unsigned char *)0xF4000009, 0x0E);
}
+
+void
+board_init2(void)
+{
+}
diff --git a/src/mainboard/motorola/sandpoint/init.c b/src/mainboard/motorola/sandpoint/init.c
index 3a9993d785..816412b8f7 100644
--- a/src/mainboard/motorola/sandpoint/init.c
+++ b/src/mainboard/motorola/sandpoint/init.c
@@ -45,14 +45,11 @@ void pnp_output(char address, char data)
void
board_init(void)
{
- /*
- * Configure FLASH
- */
+}
- /*
- * Configure NVTRC/BCSR
- */
-
+void
+board_init2(void)
+{
/*
* Enable UART0
*
@@ -67,5 +64,5 @@ board_init(void)
pnp_output(0x61, TTYS0_BASE & 0xFF); /* IO Base */
pnp_output(0x30, 1); /* Activate */
uart8250_init(TTYS0_BASE, 115200/TTYS0_BAUD, TTYS0_LCS);
- printk_info("Board initialized...\n");
+ printk_info("Sandpoint initialized...\n");
}
diff --git a/src/mainboard/totalimpact/briq/init.c b/src/mainboard/totalimpact/briq/init.c
index 22e7c1370b..d3c5b1959d 100644
--- a/src/mainboard/totalimpact/briq/init.c
+++ b/src/mainboard/totalimpact/briq/init.c
@@ -32,10 +32,15 @@
void
board_init(void)
{
+}
+
+void
+board_init2(void)
+{
/*
* Enable UART
*/
uart8250_init(TTYS0_BASE, TTYS0_DIV, TTYS0_LCS);
- printk_info("briQ board initialized...\n");
+ printk_info("briQ initialized...\n");
}
diff --git a/src/northbridge/ibm/cpc710/cpc710.c b/src/northbridge/ibm/cpc710/cpc710.c
index 121ecef690..8821850281 100644
--- a/src/northbridge/ibm/cpc710/cpc710.c
+++ b/src/northbridge/ibm/cpc710/cpc710.c
@@ -10,6 +10,7 @@
CPC710_MCCR_FIXED_BITS
void cpc710_init(void);
+void sdram_init(void);
extern void cpc710_pci_init(void);
void
@@ -25,17 +26,16 @@ getCPC710(uint32_t addr)
}
void
-sdram_init(void)
+memory_init(void)
{
cpc710_init();
+ sdram_init();
cpc710_pci_init();
}
void
cpc710_init(void)
{
- uint32_t mccr;
-
setCPC710(CPC710_CPC0_RSTR, 0xf0000000);
(void)getCPC710(CPC710_CPC0_MPSR);
setCPC710(CPC710_CPC0_SIOC0, 0x00000000);
@@ -55,6 +55,12 @@ cpc710_init(void)
setCPC710(CPC710_SDRAM0_MEAR, 0x00000000);
setCPC710(CPC710_SDRAM0_MWPR, 0x00000000);
setCPC710(CPC710_CPC0_RGBAN1, 0x00000000);
+}
+
+void
+sdram_init()
+{
+ uint32_t mccr;
/*
* Reset memory configuration
diff --git a/src/northbridge/motorola/mpc107/mpc107.c b/src/northbridge/motorola/mpc107/mpc107.c
index 00c38e5a0d..8fdc8a9c14 100644
--- a/src/northbridge/motorola/mpc107/mpc107.c
+++ b/src/northbridge/motorola/mpc107/mpc107.c
@@ -35,7 +35,7 @@
void mpc107_init(void);
void
-sdram_init(void)
+memory_init(void)
{
struct sdram_dimm_info dimms[NUM_DIMMS];
struct sdram_bank_info banks[NUM_BANKS];