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| author | Werner Zeh <werner.zeh@siemens.com> | 2017-07-21 10:22:47 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2017-07-26 04:37:13 +0000 |
| commit | ab94ba309e13b14334ed4dcf443d11e0e5baeb61 (patch) | |
| tree | 33b66daa14ba7e2055035f784f4fd84c5abcb1af /src | |
| parent | e4ff2b75fa54e12a3c5a5cc26bf7ddcba49c1698 (diff) | |
| download | coreboot-ab94ba309e13b14334ed4dcf443d11e0e5baeb61.tar.xz | |
intel/common/block/itss: Extend itss_irq_init() to handle IOSF 1.0
Current implementation of itss_irq_init() uses 8 bit write access to
IRQ routing registers which is not supported on Apollo Lake.
This commit moves the register access from 8 bit to 32 bit so that this
function can be used with every platform.
Change-Id: I15c3c33a16329fd57f0ad7f99d720adbf300d094
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/common/block/itss/itss.c | 34 |
1 files changed, 22 insertions, 12 deletions
diff --git a/src/soc/intel/common/block/itss/itss.c b/src/soc/intel/common/block/itss/itss.c index a217675405..a8b390b719 100644 --- a/src/soc/intel/common/block/itss/itss.c +++ b/src/soc/intel/common/block/itss/itss.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,18 +24,27 @@ void itss_irq_init(uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]) { - uint8_t index = 0; - - for (index = 0; index < MAX_PXRC_CONFIG; index++) { - uint8_t val = pch_interrupt_routing[index]; - uint8_t irq = val & 0xf; - - if (irq == 8 || irq == 13) - continue; - if (irq <= 2) - continue; - - pcr_write8(PID_ITSS, PCR_ITSS_PIRQA_ROUT + index, val); + uint32_t regs[MAX_PXRC_CONFIG/sizeof(uint32_t)] = {0}; + uint8_t index, byte; + + /* Fill in all the PIRx routes into one array. */ + for (index = 0; index < ARRAY_SIZE(regs); index++) { + for (byte = 0; byte < sizeof(uint32_t); byte++) { + uint8_t val = pch_interrupt_routing[index * + sizeof(uint32_t) + byte]; + uint8_t irq = val & 0xf; + + if ((irq <= 2) || (irq == 8) || (irq == 13)) + regs[index] |= (0x80 << (8 * byte)); + else + regs[index] |= (val << (8 * byte)); + } + /* Access the routing register in 32 bit mode to make this + function suitable for both IOSF 1.0 (where only 32 bit access + is supported) and later versions of the interface. */ + pcr_write32(PID_ITSS, + PCR_ITSS_PIRQA_ROUT + (index * sizeof(uint32_t)), + regs[index]); } } |