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authorMatt Papageorge <matthewpapa07@gmail.com>2020-07-30 15:22:46 -0500
committerFurquan Shaikh <furquan@google.com>2020-08-28 17:50:50 +0000
commitb87effe1dde3cc3f81a6afef073009ba808e11a7 (patch)
tree5c7af146e915094379da2ff00aa46af2e76c7c67 /src
parentb1c7ed326a2f49997fef537f925e8fb883dc3d0c (diff)
downloadcoreboot-b87effe1dde3cc3f81a6afef073009ba808e11a7.tar.xz
soc/amd/picasso/romstage: Set SATA enable UPD if controller is enabled
FSP has recently added support for a UPD switch to power gate SATA. This change adds the coreboot side of the feature. To avoid having two SATA enable options, the value of the sata_enable UPD is determined by the enable state of the AHCI controller in the platform devicetree. BUG=b:162302027 BRANCH=zork TEST=Verify AHCI controller can be hidden/disabled. Change-Id: I48bf94a7e6249db6079a6e3de7456a536d54a242 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44067 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/picasso/romstage.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index 0accc49cfa..b96743101c 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -64,6 +64,29 @@ static bool devtree_hda_dev_enabled(void)
}
+static const struct device_path sata_path[] = {
+ {
+ .type = DEVICE_PATH_PCI,
+ .pci.devfn = PCIE_GPP_B_DEVFN
+ },
+ {
+ .type = DEVICE_PATH_PCI,
+ .pci.devfn = SATA_DEVFN
+ },
+};
+
+static bool devtree_sata_dev_enabled(void)
+{
+ const struct device *ahci_dev;
+
+ ahci_dev = find_dev_nested_path(pci_root_bus(), sata_path, ARRAY_SIZE(sata_path));
+
+ if (!ahci_dev)
+ return false;
+
+ return ahci_dev->enabled;
+}
+
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
FSP_M_CONFIG *mcfg = &mupd->FspmConfig;
@@ -115,6 +138,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
mcfg->telemetry_vddcr_soc_slope = config->telemetry_vddcr_soc_slope;
mcfg->telemetry_vddcr_soc_offset = config->telemetry_vddcr_soc_offset;
mcfg->hd_audio_enable = devtree_hda_dev_enabled();
+ mcfg->sata_enable = devtree_sata_dev_enabled();
}
asmlinkage void car_stage_entry(void)