diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-20 15:49:59 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-20 15:49:59 +0000 |
| commit | b9aea8933c754295436d58027b5b43065bd59c90 (patch) | |
| tree | 4d271a90c29c14b68c4e863416d798284d3b66fb /src | |
| parent | 169dc7e5ac948ccaecadcfd243551f4247df866d (diff) | |
| download | coreboot-b9aea8933c754295436d58027b5b43065bd59c90.tar.xz | |
cosmetics.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/amd/lx/pll_reset.c | 18 | ||||
| -rw-r--r-- | src/northbridge/amd/lx/raminit.c | 7 |
2 files changed, 9 insertions, 16 deletions
diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c index 576a2239ed..1f8e499825 100644 --- a/src/northbridge/amd/lx/pll_reset.c +++ b/src/northbridge/amd/lx/pll_reset.c @@ -24,17 +24,13 @@ static void pll_reset(char manualconf) msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL); - print_debug("_MSR GLCP_SYS_RSTPLL ("); - print_debug_hex32(GLCP_SYS_RSTPLL); - print_debug(") value is: "); - print_debug_hex32(msrGlcpSysRstpll.hi); - print_debug(":"); - print_debug_hex32(msrGlcpSysRstpll.lo); - print_debug("\n"); + printk(BIOS_DEBUG, "MSR GLCP_SYS_RSTPLL (%08x) value is %08x:%08x\n", + GLCP_SYS_RSTPLL, msrGlcpSysRstpll.hi, msrGlcpSysRstpll.lo); + post_code(POST_PLL_INIT); if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) { - print_debug("Configuring PLL\n"); + printk(BIOS_DEBUG, "Configuring PLL.\n"); if (manualconf) { post_code(POST_PLL_MANUAL); /* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */ @@ -62,13 +58,13 @@ static void pll_reset(char manualconf) msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET; wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll); - /* You should never get here..... The chip has reset. */ - print_debug("CONFIGURING PLL FAILURE\n"); + /* You should never get here..... The chip has reset. */ + printk(BIOS_ERR, "CONFIGURING PLL FAILURE\n"); post_code(POST_PLL_RESET_FAIL); __asm__ __volatile__("hlt\n"); } - print_debug("Done pll_reset\n"); + printk(BIOS_DEBUG, "PLL configured.\n"); return; } diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c index bf7a817c80..75d77f0305 100644 --- a/src/northbridge/amd/lx/raminit.c +++ b/src/northbridge/amd/lx/raminit.c @@ -29,10 +29,7 @@ static const unsigned char NumColAddr[] = { static void banner(const char *s) { - /* This is so ugly. */ - print_debug("==========================="); - print_debug(s); - print_debug("======================================\n"); + printk(BIOS_DEBUG, " * %s\n", s); } static void hcf(void) @@ -572,7 +569,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) { uint8_t spd_byte; - banner("sdram_set_spd_register\n"); + banner("sdram_set_spd_register"); post_code(POST_MEM_SETUP); // post_70h spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES); |