summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorVadim Bendebury <vbendeb@chromium.org>2017-02-14 10:48:11 +0800
committerAaron Durbin <adurbin@chromium.org>2017-04-24 22:33:06 +0200
commitc77259c4e5e02fcf829afe9bf437b70dbddcbf3c (patch)
tree231a90a203c33e3210c7d40c9c208131b76aa328 /src
parent50340f5480c943b6434c9b5e6178731a9977cae3 (diff)
downloadcoreboot-c77259c4e5e02fcf829afe9bf437b70dbddcbf3c.tar.xz
google/oak: Support cr50 over I2C on rowan
This patch enables TPM2 using cr50 over I2C for the Rowan board, and adds an mt8173 specific TPM IRQ polling function. The function relies on the appropriate EINT input configured to trigger the ready status on the rising edge. The cr50 TPM is on I2C address 0x50. The cr50 interrupt GPIO is also made available for use by depthcharge via the coreboot tables. BRANCH=none BUG=b:36786804 TEST=Boot rowan w/ serial enabled, verify coreboot and depthcharge are configured to use IRQ flow control when talking to the Cr50 TPM. Change-Id: If6cdd0e39e4ac86538f27f322c55c329179ee084 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/19364 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/oak/Kconfig9
-rw-r--r--src/mainboard/google/oak/Makefile.inc4
-rw-r--r--src/mainboard/google/oak/bootblock.c3
-rw-r--r--src/mainboard/google/oak/chromeos.c1
-rw-r--r--src/mainboard/google/oak/gpio.h2
-rw-r--r--src/mainboard/google/oak/tpm_tis.c24
-rw-r--r--src/soc/mediatek/mt8173/Makefile.inc1
7 files changed, 43 insertions, 1 deletions
diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig
index 28771b8dd7..d727ffca92 100644
--- a/src/mainboard/google/oak/Kconfig
+++ b/src/mainboard/google/oak/Kconfig
@@ -18,6 +18,12 @@ config BOARD_GOOGLE_OAK_COMMON
if BOARD_GOOGLE_OAK_COMMON
+config OAK_HAS_TPM2
+ bool
+ default y if BOARD_GOOGLE_ROWAN
+ default n
+ select MAINBOARD_HAS_I2C_TPM_CR50
+
config BOARD_SPECIFIC_OPTIONS
def_bool y
select SOC_MEDIATEK_MT8173
@@ -56,7 +62,8 @@ config DRIVER_TPM_I2C_BUS
config DRIVER_TPM_I2C_ADDR
hex
- default 0x20
+ default 0x20 if !OAK_HAS_TPM2
+ default 0x50 if OAK_HAS_TPM2
config BOOT_DEVICE_SPI_FLASH_BUS
int
diff --git a/src/mainboard/google/oak/Makefile.inc b/src/mainboard/google/oak/Makefile.inc
index f32b7a7418..aa7abc27f0 100644
--- a/src/mainboard/google/oak/Makefile.inc
+++ b/src/mainboard/google/oak/Makefile.inc
@@ -17,16 +17,20 @@ bootblock-y += bootblock.c
bootblock-y += memlayout.ld
bootblock-y += chromeos.c
bootblock-y += boardid.c
+bootblock-$(CONFIG_OAK_HAS_TPM2) += tpm_tis.c
verstage-y += chromeos.c
verstage-y += memlayout.ld
+verstage-$(CONFIG_OAK_HAS_TPM2) += tpm_tis.c
romstage-y += chromeos.c
romstage-y += romstage.c sdram_configs.c
romstage-y += memlayout.ld
romstage-y += boardid.c
+romstage-$(CONFIG_OAK_HAS_TPM2) += tpm_tis.c
ramstage-y += mainboard.c
ramstage-y += chromeos.c
ramstage-y += memlayout.ld
ramstage-y += boardid.c
+ramstage-$(CONFIG_OAK_HAS_TPM2) += tpm_tis.c
diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c
index 04a3a550ec..fe9c9ba8c4 100644
--- a/src/mainboard/google/oak/bootblock.c
+++ b/src/mainboard/google/oak/bootblock.c
@@ -88,6 +88,9 @@ void bootblock_mainboard_init(void)
/* Init i2c bus 2 Timing register for TPM */
mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS);
+ if (IS_ENABLED(CONFIG_OAK_HAS_TPM2))
+ gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING);
+
mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz);
setup_chromeos_gpios();
diff --git a/src/mainboard/google/oak/chromeos.c b/src/mainboard/google/oak/chromeos.c
index a581364d1d..42145f7f1d 100644
--- a/src/mainboard/google/oak/chromeos.c
+++ b/src/mainboard/google/oak/chromeos.c
@@ -42,6 +42,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{POWER_BUTTON, ACTIVE_HIGH, -1, "power"},
{EC_IN_RW, ACTIVE_HIGH, -1, "EC in RW"},
{EC_IRQ, ACTIVE_LOW, -1, "EC interrupt"},
+ {CR50_IRQ, ACTIVE_HIGH, -1, "TPM interrupt"},
};
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
diff --git a/src/mainboard/google/oak/gpio.h b/src/mainboard/google/oak/gpio.h
index 3c0f51afb6..35f47c6b6e 100644
--- a/src/mainboard/google/oak/gpio.h
+++ b/src/mainboard/google/oak/gpio.h
@@ -42,6 +42,8 @@ enum {
EC_IN_RW = PAD_DAIPCMIN,
/* EC AP suspend */
EC_SUSPEND_L = PAD_KPROW1,
+ /* Cr50 interrupt */
+ CR50_IRQ = PAD_EINT16,
};
void setup_chromeos_gpios(void);
diff --git a/src/mainboard/google/oak/tpm_tis.c b/src/mainboard/google/oak/tpm_tis.c
new file mode 100644
index 0000000000..018f02db10
--- /dev/null
+++ b/src/mainboard/google/oak/tpm_tis.c
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <gpio.h>
+#include <tpm.h>
+
+#include "gpio.h"
+
+int tis_plat_irq_status(void)
+{
+ return gpio_eint_poll(CR50_IRQ);
+}
diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc
index b79492d19c..fecd7f165e 100644
--- a/src/soc/mediatek/mt8173/Makefile.inc
+++ b/src/soc/mediatek/mt8173/Makefile.inc
@@ -40,6 +40,7 @@ verstage-$(CONFIG_DRIVERS_UART) += uart.c
verstage-y += timer.c
verstage-y += wdt.c
verstage-$(CONFIG_SPI_FLASH) += flash_controller.c
+verstage-y += gpio.c
################################################################################