diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2018-04-17 11:45:32 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-04-23 09:18:50 +0000 |
| commit | c82e48d7e4266d2333c78bf7f841e749beec40b8 (patch) | |
| tree | 2fd709c710c2241f42788f5772ea5f8ef5f7d943 /src | |
| parent | d5e4746cf84a8da1b6465058ec7c7cc19c3c32c0 (diff) | |
| download | coreboot-c82e48d7e4266d2333c78bf7f841e749beec40b8.tar.xz | |
cpu/x86: add paging_set_default_pat() function
Add paging_set_default_pat() which sets up the PAT MSR according
to util/x86/x86_page_tables.go. Using page attribute types require
a matching of the PAT values with the page table entries. This function
is just providing the default PAT MSR value to match against the
utility.
BUG=b:72728953
Change-Id: I7ed34a3565647ffc359ff102d3f6a59fbc93cc22
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/x86/pae/pgtbl.c | 25 | ||||
| -rw-r--r-- | src/include/cpu/x86/pae.h | 10 |
2 files changed, 35 insertions, 0 deletions
diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index fe7705f4d0..cd03547ef8 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -144,3 +144,28 @@ void paging_set_pat(uint64_t pat) msr.hi = pat >> 32; wrmsr(MSR_IA32_PAT, msr); } + +/* PAT encoding used in util/x86/x86_page_tables.go. It matches the linux + * kernel settings: + * PTE encoding: + * PAT + * |PCD + * ||PWT PAT + * ||| slot + * 000 0 WB : _PAGE_CACHE_MODE_WB + * 001 1 WC : _PAGE_CACHE_MODE_WC + * 010 2 UC-: _PAGE_CACHE_MODE_UC_MINUS + * 011 3 UC : _PAGE_CACHE_MODE_UC + * 100 4 WB : Reserved + * 101 5 WP : _PAGE_CACHE_MODE_WP + * 110 6 UC-: Reserved + * 111 7 WT : _PAGE_CACHE_MODE_WT + */ +void paging_set_default_pat(void) +{ + uint64_t pat = PAT_ENCODE(WB, 0) | PAT_ENCODE(WC, 1) | + PAT_ENCODE(UC_MINUS, 2) | PAT_ENCODE(UC, 3) | + PAT_ENCODE(WB, 4) | PAT_ENCODE(WP, 5) | + PAT_ENCODE(UC_MINUS, 6) | PAT_ENCODE(WT, 7); + paging_set_pat(pat); +} diff --git a/src/include/cpu/x86/pae.h b/src/include/cpu/x86/pae.h index 5bbfdf3aca..96999bb0a8 100644 --- a/src/include/cpu/x86/pae.h +++ b/src/include/cpu/x86/pae.h @@ -14,8 +14,18 @@ void paging_disable_pae(void); /* Set/Clear NXE bit in IA32_EFER MSR */ void paging_set_nxe(int enable); +#define PAT_UC 0 +#define PAT_WC 1 +#define PAT_WT 4 +#define PAT_WP 5 +#define PAT_WB 6 +#define PAT_UC_MINUS 7 +#define PAT_ENCODE(type, idx) (((uint64_t)PAT_ ## type) << 8*(idx)) + /* Set PAT MSR */ void paging_set_pat(uint64_t pat); +/* Set coreboot default PAT value. */ +void paging_set_default_pat(void); #define MAPPING_ERROR ((void *)0xffffffffUL) void *map_2M_page(unsigned long page); |