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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-18 16:33:06 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-20 01:31:44 +0000
commitcd2aa47a340432503ba67672e19931ed2f3296bf (patch)
tree297246cf5bd867066f5a7e6818cd16bec0521328 /src
parent216f717d315eccc5b33827627b784c06ca8248e8 (diff)
downloadcoreboot-cd2aa47a340432503ba67672e19931ed2f3296bf.tar.xz
devicetree: Remove duplicate chip_ops declarations
These are only referenced inside auto-generated static.c files, and util/sconfig also generates the declarations automatically from source file pathnames. Change-Id: Id324790755095c36fbeb73a4d8f9d01cdf6409cb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34979 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/cpu/intel/haswell/chip.h2
-rw-r--r--src/ec/compal/ene932/chip.h5
-rw-r--r--src/ec/google/chromeec/chip.h3
-rw-r--r--src/ec/google/wilco/chip.h4
-rw-r--r--src/ec/quanta/ene_kb3940q/chip.h5
-rw-r--r--src/ec/quanta/it8518/chip.h5
-rw-r--r--src/ec/roda/it8518/chip.h5
-rw-r--r--src/northbridge/intel/haswell/chip.h2
-rw-r--r--src/soc/intel/baytrail/chip.h1
-rw-r--r--src/soc/intel/braswell/chip.h2
-rw-r--r--src/soc/intel/broadwell/chip.h2
-rw-r--r--src/soc/intel/denverton_ns/chip.h2
-rw-r--r--src/soc/intel/fsp_baytrail/chip.h1
-rw-r--r--src/soc/intel/fsp_broadwell_de/chip.h1
-rw-r--r--src/soc/intel/quark/chip.h2
-rw-r--r--src/soc/intel/skylake/chip.h2
16 files changed, 0 insertions, 44 deletions
diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h
index cd9ec5d51b..b2cb33be03 100644
--- a/src/cpu/intel/haswell/chip.h
+++ b/src/cpu/intel/haswell/chip.h
@@ -13,8 +13,6 @@
* GNU General Public License for more details.
*/
-extern struct chip_operations cpu_intel_haswell_ops;
-
/* Magic value used to locate this chip in the device tree */
#define SPEEDSTEP_APIC_MAGIC 0xACAC
diff --git a/src/ec/compal/ene932/chip.h b/src/ec/compal/ene932/chip.h
index c7e4f8d9be..94f975282b 100644
--- a/src/ec/compal/ene932/chip.h
+++ b/src/ec/compal/ene932/chip.h
@@ -17,11 +17,6 @@
#ifndef _EC_COMPAL_ENE932_CHIP_H
#define _EC_COMPAL_ENE932_CHIP_H
-#include <device/device.h>
-
-struct chip_operations;
-extern struct chip_operations ec_compal_ene932_ops;
-
struct ec_compal_ene932_config {
};
diff --git a/src/ec/google/chromeec/chip.h b/src/ec/google/chromeec/chip.h
index 4eada16b0d..1c9a7f59e7 100644
--- a/src/ec/google/chromeec/chip.h
+++ b/src/ec/google/chromeec/chip.h
@@ -16,9 +16,6 @@
#ifndef EC_GOOGLE_CHROMEEC_CHIP_H
#define EC_GOOGLE_CHROMEEC_CHIP_H
-#include <device/device.h>
-
-extern struct chip_operations ec_google_chromeec_ops;
struct ec_google_chromeec_config {
};
diff --git a/src/ec/google/wilco/chip.h b/src/ec/google/wilco/chip.h
index 9b02ee346d..06d889c108 100644
--- a/src/ec/google/wilco/chip.h
+++ b/src/ec/google/wilco/chip.h
@@ -16,10 +16,6 @@
#ifndef EC_GOOGLE_WILCO_CHIP_H
#define EC_GOOGLE_WILCO_CHIP_H
-#include <device/device.h>
-
-extern struct chip_operations ec_google_wilco_ops;
-
struct ec_google_wilco_config {
};
diff --git a/src/ec/quanta/ene_kb3940q/chip.h b/src/ec/quanta/ene_kb3940q/chip.h
index 8348cc09ef..b812a18b36 100644
--- a/src/ec/quanta/ene_kb3940q/chip.h
+++ b/src/ec/quanta/ene_kb3940q/chip.h
@@ -17,11 +17,6 @@
#ifndef _EC_QUANTA_ENE_KB3940Q_CHIP_H
#define _EC_QUANTA_ENE_KB3940Q_CHIP_H
-#include <device/device.h>
-
-struct chip_operations;
-extern struct chip_operations ec_quanta_ene_kb3940q_ops;
-
struct ec_quanta_ene_kb3940q_config {
};
diff --git a/src/ec/quanta/it8518/chip.h b/src/ec/quanta/it8518/chip.h
index ea9b4ac779..5dd14f6b29 100644
--- a/src/ec/quanta/it8518/chip.h
+++ b/src/ec/quanta/it8518/chip.h
@@ -17,11 +17,6 @@
#ifndef _EC_QUANTA_IT8518_CHIP_H
#define _EC_QUANTA_IT8518_CHIP_H
-#include <device/device.h>
-
-struct chip_operations;
-extern struct chip_operations ec_quanta_it8518_ops;
-
struct ec_quanta_it8518_config {
};
diff --git a/src/ec/roda/it8518/chip.h b/src/ec/roda/it8518/chip.h
index 44891e84fa..8091525e9b 100644
--- a/src/ec/roda/it8518/chip.h
+++ b/src/ec/roda/it8518/chip.h
@@ -16,11 +16,6 @@
#ifndef _EC_RODA_IT8518_CHIP_H
#define _EC_RODA_IT8518_CHIP_H
-#include <device/device.h>
-
-struct chip_operations;
-extern struct chip_operations ec_roda_it8518_ops;
-
struct ec_roda_it8518_config {
u8 cpuhot_limit; /* temperature in °C which asserts PROCHOT# */
};
diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h
index fdabc3fc9a..506aaa58e8 100644
--- a/src/northbridge/intel/haswell/chip.h
+++ b/src/northbridge/intel/haswell/chip.h
@@ -45,6 +45,4 @@ struct northbridge_intel_haswell_config {
struct i915_gpu_controller_info gfx;
};
-extern struct chip_operations northbridge_intel_haswell_ops;
-
#endif /* NORTHBRIDGE_INTEL_HASWELL_CHIP_H */
diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h
index 00e7fd6f73..f153913a0f 100644
--- a/src/soc/intel/baytrail/chip.h
+++ b/src/soc/intel/baytrail/chip.h
@@ -87,5 +87,4 @@ struct soc_intel_baytrail_config {
int disable_ddr_2x_refresh_rate;
};
-extern struct chip_operations soc_intel_baytrail_ops;
#endif /* _BAYTRAIL_CHIP_H_ */
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index 5a00328f4d..747b941f55 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -171,6 +171,4 @@ struct soc_intel_braswell_config {
UINT8 I2C6Frequency;
};
-extern struct chip_operations soc_intel_braswell_ops;
-
#endif /* _SOC_CHIP_H_ */
diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h
index 0885c2dd5b..456a4354ca 100644
--- a/src/soc/intel/broadwell/chip.h
+++ b/src/soc/intel/broadwell/chip.h
@@ -164,6 +164,4 @@ struct soc_intel_broadwell_config {
typedef struct soc_intel_broadwell_config config_t;
-extern struct chip_operations soc_ops;
-
#endif
diff --git a/src/soc/intel/denverton_ns/chip.h b/src/soc/intel/denverton_ns/chip.h
index f2a67dd9f9..53e86f97b0 100644
--- a/src/soc/intel/denverton_ns/chip.h
+++ b/src/soc/intel/denverton_ns/chip.h
@@ -72,8 +72,6 @@ struct soc_intel_denverton_ns_config {
uint32_t ipc3;
};
-extern struct chip_operations soc_intel_denverton_ns_ops;
-
typedef struct soc_intel_denverton_ns_config config_t;
#endif /* SOC_INTEL_FSP_DENVERTON_NS_CHIP_H */
diff --git a/src/soc/intel/fsp_baytrail/chip.h b/src/soc/intel/fsp_baytrail/chip.h
index 156a08434c..b73aa14904 100644
--- a/src/soc/intel/fsp_baytrail/chip.h
+++ b/src/soc/intel/fsp_baytrail/chip.h
@@ -353,5 +353,4 @@ struct soc_intel_fsp_baytrail_config {
};
-extern struct chip_operations soc_intel_fsp_baytrail_ops;
#endif /* _FSP_BAYTRAIL_CHIP_H_ */
diff --git a/src/soc/intel/fsp_broadwell_de/chip.h b/src/soc/intel/fsp_broadwell_de/chip.h
index b7f59f7f12..bf2896238a 100644
--- a/src/soc/intel/fsp_broadwell_de/chip.h
+++ b/src/soc/intel/fsp_broadwell_de/chip.h
@@ -29,5 +29,4 @@ struct soc_intel_fsp_broadwell_de_config {
typedef struct soc_intel_fsp_broadwell_de_config config_t;
-extern struct chip_operations soc_intel_fsp_broadwell_de_ops;
#endif /* _SOC_CHIP_H_ */
diff --git a/src/soc/intel/quark/chip.h b/src/soc/intel/quark/chip.h
index 25d734a7df..4e57273ffe 100644
--- a/src/soc/intel/quark/chip.h
+++ b/src/soc/intel/quark/chip.h
@@ -113,6 +113,4 @@ struct soc_intel_quark_config {
uint8_t SmmTsegSize; /* SMM size in MiB */
};
-extern struct chip_operations soc_ops;
-
#endif
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 6c105cea8c..1313dc15b9 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -591,6 +591,4 @@ struct soc_intel_skylake_config {
typedef struct soc_intel_skylake_config config_t;
-extern struct chip_operations soc_ops;
-
#endif