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| author | Nico Huber <nico.huber@secunet.com> | 2012-11-13 14:45:38 +0100 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-11-14 17:46:09 +0100 |
| commit | d172497dee39a169d9088a92ec1ff25ecc24a710 (patch) | |
| tree | 47e60d8d44b784bdbdc67d7f2627a551a9251b2c /src | |
| parent | 6e711c6a97a9d4122615018121d0d2a37b642ed1 (diff) | |
| download | coreboot-d172497dee39a169d9088a92ec1ff25ecc24a710.tar.xz | |
mainboard/siemens/sitemp_g1p1: Fix CMOS checksum algorithm here, too
Some time ago our CMOS checksum algorithm was changed under the topic:
Fix our CMOS checksum algorithm so it matches what /dev/nvram expects
Here is another copy of the algorithm that had to be updated.
Change-Id: I58659c7b8a89c89c76efdff405ee0620e7302277
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1852
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/siemens/sitemp_g1p1/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 0c61e5d3fc..141b0fae7f 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -147,7 +147,7 @@ static inline int cmos_chksum_valid(void) { #if DUMP_CMOS_RAM __DEBUG__("\n"); #endif - sum = (sum & 0xffff) ^ 0xffff; + sum = (sum & 0xffff); /* Read the stored checksum */ outb(LB_CKS_LOC, 0x72); |