diff options
| author | jinkun.hong <jinkun.hong@rock-chips.com> | 2015-01-21 16:03:43 +0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-04-15 22:09:55 +0200 |
| commit | d4a227ba05aadf049cec0b4e4edc8345f476c2f4 (patch) | |
| tree | 2a6b6b260b8d0cae28a4094c6dcbe080e5bb13aa /src | |
| parent | 29bd9e2c74b7d4c381cae240d561bad291a67c71 (diff) | |
| download | coreboot-d4a227ba05aadf049cec0b4e4edc8345f476c2f4.tar.xz | |
rk3288: Fix failing DDR3 reboot test
We want a reset signal to last 200us. The length of a reset signal is
represented by BIT0~BIT16 in DDR_PUBL_PTR2. When DDR memory runs at
667MHz, the calculated value for the reset signal is 0x20850, which is
bigger than the maximum value that can be described with 17 bits
(0x1ffff). As a result, the memory controller only sees 0x850, which
generates a 3.5us reset cycle instead, which violates the standard and
negatively impacts memory stability.
So instead, we now set it to the maximum value (0x1ffff) to prevent this
overflow, resulting in a reset signal of 196us for 667MHz DDR memory.
BUG=chrome-os-partner:34875
TEST=loop reboot
BRANCH=veyron
Change-Id: Ia01f8a0414b49fa3ecf4d543cfa1822e29ee4cc4
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 767a4a3cb8dff47cb15064d335b78ffa5815914d
Original-Change-Id: I9b410e1605c87f12a5ca96ead12f8527ca4f417f
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/242175
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9653
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/rockchip/rk3288/sdram.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c index 5a158adb72..d330f99d6e 100644 --- a/src/soc/rockchip/rk3288/sdram.c +++ b/src/soc/rockchip/rk3288/sdram.c @@ -639,6 +639,7 @@ static void pctl_cfg(u32 channel, static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) { u32 i; + u32 dinit2 = div_round_up(sdram_params->ddr_freq/MHz * 200000, 1000); struct rk3288_ddr_publ_regs *ddr_publ_regs = rk3288_ddr_publ[channel]; struct rk3288_msch_regs *msch_regs = rk3288_msch[channel]; @@ -660,8 +661,7 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) * 500000, 1000)) | PRT_DINIT1(div_round_up(sdram_params->ddr_freq/MHz * 400, 1000)), &ddr_publ_regs->ptr[1]); - writel(PRT_DINIT2(div_round_up(sdram_params->ddr_freq/MHz - * 200000, 1000)) + writel(PRT_DINIT2(MIN(dinit2, 0x1ffff)) | PRT_DINIT3(div_round_up(sdram_params->ddr_freq/MHz * 1000, 1000)), &ddr_publ_regs->ptr[2]); |