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authorpeichao.wang <peichao.wang@bitland.corp-partner.google.com>2018-10-09 12:18:31 +0800
committerAaron Durbin <adurbin@chromium.org>2018-10-10 18:38:38 +0000
commitd5325ddcc27535e13a224cb62759933186de0d39 (patch)
tree925ae6fa146ce56010b7d29a4e5a4a25ed4fd1c7 /src
parent4b6f262eadeddfd1f333f7ce05b2a46a5f39b8bf (diff)
downloadcoreboot-d5325ddcc27535e13a224cb62759933186de0d39.tar.xz
mb/google/octopus: Drop I2C bus 0 clock frequency for Phaser
Need to tune I2C bus 0 clock frequency under the 400KHz since this bus attached the Stylus EMR pen and need meet the spec. Bug=b:117297214 TEST=flash coreboot to the DUT and measure I2C bus 0 clock frequency whether under 400KHz Change-Id: I06d9d25f52d7f641d937de0d6b7df3d7a076fbf9 Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28973 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/octopus/variants/phaser/overridetree.cb4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/octopus/variants/phaser/overridetree.cb b/src/mainboard/google/octopus/variants/phaser/overridetree.cb
index 2f6915e62a..3a208ea600 100644
--- a/src/mainboard/google/octopus/variants/phaser/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/phaser/overridetree.cb
@@ -20,8 +20,8 @@ chip soc/intel/apollolake
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
- .rise_time_ns = 152,
- .fall_time_ns = 30,
+ .rise_time_ns = 66,
+ .fall_time_ns = 90,
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,