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authorMarshall Dawson <marshalldawson3rd@gmail.com>2017-11-29 09:46:28 -0700
committerMartin Roth <martinroth@google.com>2018-01-19 19:48:08 +0000
commitd77c764dd1181204b6682b657e561d0a929cf4c7 (patch)
tree019a002cadc4340c674a9ab3710f4033f636ce81 /src
parent3a7de79885e693526f33e892de095b980116ac49 (diff)
downloadcoreboot-d77c764dd1181204b6682b657e561d0a929cf4c7.tar.xz
amd/stoneyridge: Move SB index/data pairs to iomap.h
Relocate the I/O registers to the iomap for PM, PM2, and BIOSRAM. Change-Id: I3a59adc974a8a90bfc586188b829a7252356b3cb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22723 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/stoneyridge/include/soc/iomap.h6
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h9
2 files changed, 7 insertions, 8 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h
index ac340a62af..2d42ad9ad9 100644
--- a/src/soc/amd/stoneyridge/include/soc/iomap.h
+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h
@@ -51,6 +51,12 @@
#define ACPI_GPE0_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */
#define ACPI_PM_TMR_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */
#define SMB_BASE_ADDR 0xb00
+#define PM2_INDEX 0xcd0
+#define PM2_DATA 0xcd1
+#define BIOSRAM_INDEX 0xcd4
+#define BIOSRAM_DATA 0xcd5
+#define PM_INDEX 0xcd6
+#define PM_DATA 0xcd7
#define AB_INDX 0xcd8
#define AB_DATA (AB_INDX+4)
#define SYS_RESET 0xcf9
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index d9016bc427..73e9b6fcd5 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -30,14 +30,7 @@
#define PSP_BAR_ENABLES 0x48
#define PSP_MAILBOX_BAR_EN 0x10
-/* Power management index/data registers */
-#define BIOSRAM_INDEX 0xcd4
-#define BIOSRAM_DATA 0xcd5
-#define PM_INDEX 0xcd6
-#define PM_DATA 0xcd7
-#define PM2_INDEX 0xcd0
-#define PM2_DATA 0xcd1
-
+/* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */
#define PM_PCI_CTRL 0x08
#define FORCE_SLPSTATE_RETRY BIT(25)
#define FORCE_STPCLK_RETRY BIT(24)