diff options
| author | Kerry Sheh <shekairui@gmail.com> | 2011-10-11 17:27:06 +0800 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2011-10-12 03:41:38 +0200 |
| commit | d7e856b9cb585777db591afa8d68317271d5aff5 (patch) | |
| tree | ba5936740a2abf3632fe11d777d638edf5e5337c /src | |
| parent | 2c7c37a01615a8435d13bd0a027ecc9b5985d7a8 (diff) | |
| download | coreboot-d7e856b9cb585777db591afa8d68317271d5aff5.tar.xz | |
sb800: Add Kconfig option ENABLE_IDE_COMBINED_MODE
Add this option to enable/disable SATA IDE Combined Mode feature
Change-Id: I1ab8acd27947a71baf954f44d0741f81f48e5541
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/231
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/Kconfig | 16 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/cfg.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/late.c | 5 |
3 files changed, 17 insertions, 6 deletions
diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index b7ac0dbf02..17ff3f9d68 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -28,6 +28,22 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/amd/cimx/sb800/bootblock.c" +config ENABLE_IDE_COMBINED_MODE + bool "Enable SATA IDE combined mode" + default n + help + If Combined Mode is enabled. IDE controller is exposed and + SATA controller has control over Port0 through Port3, + IDE controller has control over Port4 and Port5. + + If Combined Mode is disabled, IDE controller is hidden and + SATA controller has full control of all 6 Ports when operating in non-IDE mode. + +config IDE_COMBINED_MODE + hex + default "0x0" if ENABLE_IDE_COMBINED_MODE + default "0x1" if !ENABLE_IDE_COMBINED_MODE + choice prompt "SATA Mode" default SB800_SATA_IDE diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index a7801a8fc5..a34dd14baa 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -84,7 +84,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER; sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary. //TODO: set to secondary not take effect. - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = 0; //IDE controlor exposed and combined mode enabled + sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CONFIG_IDE_COMBINED_MODE; sb_config->SATAMODE.SataMode.SATARefClkSel = SATA_CLOCK_SOURCE; /* Azalia HDA */ diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index c36ee03237..b78f1ce726 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -343,11 +343,6 @@ static void sb800_enable(device_t dev) break; case (0x14 << 3) | 1: /* 0:14:1 IDE */ - if (dev->enabled) { - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_ENABLED; - } else { - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_DISABLED; - } break; case (0x14 << 3) | 2: /* 0:14:2 HDA */ |