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authorElyes HAOUAS <ehaouas@noos.fr>2019-06-10 13:47:56 +0200
committerNico Huber <nico.h@gmx.de>2019-06-15 16:31:01 +0000
commitd844431af09aafd65656f77b699c737966b30086 (patch)
tree85994ff365a99ff56d38adfab1a8295173083cec /src
parente94335e9fd00ee5c707eb927922ef09b9487c5d6 (diff)
downloadcoreboot-d844431af09aafd65656f77b699c737966b30086.tar.xz
vendorcode/agesa: Fix check for valid PhyLane
Found using GCC with flag -Wlogical-op Change-Id: Ia04ac5b1d0a4434c0ab2ca583b9b03dbfd0ffd41 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33362 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c2
-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c2
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c2
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c2
4 files changed, 4 insertions, 4 deletions
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
index ee7ef01035..c76b290727 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
@@ -202,7 +202,7 @@ PcieConfigGetNumberOfPhyLane (
IN PCIe_ENGINE_CONFIG *Engine
)
{
- if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.StartLane >= UNUSED_LANE_ID) {
+ if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.EndLane >= UNUSED_LANE_ID) {
return 0;
}
if (Engine->EngineData.StartLane > Engine->EngineData.EndLane) {
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
index 788c0b779a..dae9899683 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
@@ -178,7 +178,7 @@ PcieConfigGetNumberOfPhyLane (
IN PCIe_ENGINE_CONFIG *Engine
)
{
- if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.StartLane >= UNUSED_LANE_ID) {
+ if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.EndLane >= UNUSED_LANE_ID) {
return 0;
}
if (Engine->EngineData.StartLane > Engine->EngineData.EndLane) {
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
index 6466862194..9b7bcbded2 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
@@ -205,7 +205,7 @@ PcieConfigGetNumberOfPhyLane (
IN PCIe_ENGINE_CONFIG *Engine
)
{
- if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.StartLane >= UNUSED_LANE_ID) {
+ if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.EndLane >= UNUSED_LANE_ID) {
return 0;
}
if (Engine->EngineData.StartLane > Engine->EngineData.EndLane) {
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
index 8e5e3dd43a..27e7bcefda 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
@@ -205,7 +205,7 @@ PcieConfigGetNumberOfPhyLane (
IN PCIe_ENGINE_CONFIG *Engine
)
{
- if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.StartLane >= UNUSED_LANE_ID) {
+ if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.EndLane >= UNUSED_LANE_ID) {
return 0;
}
if (Engine->EngineData.StartLane > Engine->EngineData.EndLane) {