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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-03-16 10:31:37 -0700 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2012-03-16 23:17:53 +0100 |
| commit | dd3b227fb9158c2fc84a916cac8de1d2ec103982 (patch) | |
| tree | 4ac657ffe83c71c86ae4f3bd203d4fbf7fb3af5e /src | |
| parent | 30b46cefb54a8d98393cf4cf08b062f04e2f2ceb (diff) | |
| download | coreboot-dd3b227fb9158c2fc84a916cac8de1d2ec103982.tar.xz | |
Fix AMD Fam15 CBMEM allocation
The Fam15 northbridge.c had hardcoded the CBMEM size. It should use
the one in cbmem.h instead.
Change-Id: I8a00e05884bdb1d1a4a012433b0adfbb9eb22983
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/796
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/amd/agesa/family15/northbridge.c | 20 |
1 files changed, 9 insertions, 11 deletions
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index b0fc91d7a5..d1a322ca6c 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -28,6 +28,7 @@ #include <string.h> #include <bitops.h> #include <cpu/cpu.h> +#include <cbmem.h> #include <cpu/x86/lapic.h> @@ -624,10 +625,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) return mem_hole; } #endif -#if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; -#endif + #if CONFIG_GFXUMA == 1 extern uint64_t uma_memory_base, uma_memory_size; static void add_uma_resource(struct device *dev, int index) @@ -779,13 +777,13 @@ static void domain_set_resources(device_t dev) if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else - high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_size = HIGH_MEMORY_SIZE; printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - HIGH_TABLES_SIZE, high_tables_base); + (u32)(high_tables_size / 1024), high_tables_base); } #endif } @@ -813,11 +811,11 @@ static void domain_set_resources(device_t dev) if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else - high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_size = HIGH_MEMORY_SIZE; } #endif } |