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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-14 10:53:51 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-17 14:17:31 +0000 |
| commit | df946b8696731cda45a7e37e934307c3153b824f (patch) | |
| tree | e77ebc5be723b0f65b0bb99660ae0d736ebab11e /src | |
| parent | 76f7b79fb8d05e34ae247b77408a342a89ccf11b (diff) | |
| download | coreboot-df946b8696731cda45a7e37e934307c3153b824f.tar.xz | |
nb/intel/x4x: Issue a hard reset with empty MRC cache on warm reset
The dram controller cannot fully initialize the dram on warm
reset (receive enable calibration consistently fails) therefore
requiring cached timings.
This option is mostly useful when rebooting after having flashed a new
rom which overwrites the mrc cache region.
Change-Id: I405c0eca076fe081641ede9a670f734c98cbf8fc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/x4x/raminit.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index d41b74c8db..9d37ada38f 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -653,6 +653,11 @@ void sdram_initialize(int boot_path, const u8 *spd_map) /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); halt(); + } else if (boot_path == BOOT_PATH_WARM_RESET) { + /* On warm reset some of dram calibrations fail + and therefore requiring valid cached settings */ + outb(0xe, 0xcf9); + halt(); } ctrl_cached = NULL; } else { |