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authorJes Klinke <jbk@google.com>2020-08-19 14:01:30 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-08-21 07:49:29 +0000
commite046b71ba641c7f4740600d1f392e255ca9ad102 (patch)
treead7993aed42fb2e8a2dd33a6e8c1c0a228489775 /src
parent51593dd0c6cf1f69b813ba9c507f74f3641bdc68 (diff)
downloadcoreboot-e046b71ba641c7f4740600d1f392e255ca9ad102.tar.xz
soc/intel/tigerlake: Enable long cr50 ready pulses
A new Kconfig setting CR50_USE_LONG_INTERRUPT_PULSES controls new code running in verstage, which will program a new Cr50 register, to have Cr50 generate longer than default interrupt pulses. This needs to be selected on all Tiger Lake systems, since Tiger Lake (and likely future Intel SoCs) require at least 100us interrupt pulses. TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x BUG=b:154333137 Change-Id: I20100d72ce426203943c1788d538bb2cd9d82e11 Signed-off-by: Jes Bodi Klinke <jbk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/tigerlake/Kconfig5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 63998d4b8f..8718f97771 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -170,6 +170,11 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
+# Tiger Lake SoC requires at least 100us interrupt pulses in order to guarantee detection
+# in all low power states. Cr50 TPM, if used, needs to be told to generate longer pulses.
+config TPM_CR50
+ select CR50_USE_LONG_INTERRUPT_PULSES
+
config VBOOT
select VBOOT_SEPARATE_VERSTAGE
select VBOOT_MUST_REQUEST_DISPLAY