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authorAamir Bohra <aamir.bohra@intel.com>2019-12-06 19:37:37 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-12-11 11:38:04 +0000
commite0cdaf0b19b68644b6c398be825f94327572e056 (patch)
treef6ee82f84df13cfc0664edbbecbcdedbc61c7644 /src
parentddb4b0d576ce8a7a8f36ce8a8ebcfb871c11b18b (diff)
downloadcoreboot-e0cdaf0b19b68644b6c398be825f94327572e056.tar.xz
soc/intel/tigerlake: add soc implementation for ETR address API
Add soc_pmc_etr_addr function definition in tigerlake SOC code. The function is declared in common soc intel pmc driver. Change-Id: Icc471b16304c72a9341abdd9797ba3f8d0d3d1bc Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37555 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/tigerlake/pmutil.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c
index 53f86097ee..c163dc2f12 100644
--- a/src/soc/intel/tigerlake/pmutil.c
+++ b/src/soc/intel/tigerlake/pmutil.c
@@ -177,6 +177,12 @@ uintptr_t soc_read_pmc_base(void)
return (uintptr_t)pmc_mmio_regs();
}
+
+uint32_t *soc_pmc_etr_addr(void)
+{
+ return (uint32_t *)(soc_read_pmc_base() + ETR);
+}
+
void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
{
DEVTREE_CONST struct soc_intel_tigerlake_config *config;