diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-02-08 16:58:47 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-02-16 04:35:43 +0000 |
| commit | e1b8221498b6742cd87271d736ffc6f8f0f82633 (patch) | |
| tree | 1b3b00c8c8acdb5e298dcdc8c303f9faaa21bdce /src | |
| parent | 20123a8838e5c8cdf002237dcf68aa048dc2161b (diff) | |
| download | coreboot-e1b8221498b6742cd87271d736ffc6f8f0f82633.tar.xz | |
soc/intel/cannonlake: Update GPIO ASL
GPIO pin definition had been updated to match Cannonlake PCH-LP EDS,
hence the ACPI dsdt table will include those changes as well.
BUG=None
TEST=Build coreboot image, flah coreboot image into DUT, and target
system can boot up into OS.
Change-Id: I958e0cb71b4e656bec9bfe2d12076b577b57629b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/gpio.asl | 37 |
1 files changed, 32 insertions, 5 deletions
diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl index c2bf8d98e6..8a990b3c61 100644 --- a/src/soc/intel/cannonlake/acpi/gpio.asl +++ b/src/soc/intel/cannonlake/acpi/gpio.asl @@ -28,6 +28,8 @@ Device (GPIO) { Memory32Fixed (ReadWrite, 0, 0, COM0) Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM2) + Memory32Fixed (ReadWrite, 0, 0, COM3) Memory32Fixed (ReadWrite, 0, 0, COM4) Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) { GPIO_IRQ14 } @@ -47,11 +49,24 @@ Device (GPIO) Store (^^PCRB (PID_GPIOCOM1), BAS1) Store (GPIO_BASE_SIZE, LEN1) + /* GPIO Community 2 */ + CreateDWordField (^RBUF, ^COM2._BAS, BAS2) + CreateDWordField (^RBUF, ^COM2._LEN, LEN2) + Store (^^PCRB (PID_GPIOCOM2), BAS2) + Store (GPIO_BASE_SIZE, LEN2) + + /* GPIO Community 3 */ + CreateDWordField (^RBUF, ^COM3._BAS, BAS3) + CreateDWordField (^RBUF, ^COM3._LEN, LEN3) + Store (^^PCRB (PID_GPIOCOM3), BAS3) + Store (GPIO_BASE_SIZE, LEN3) + + /* GPIO Community 4 */ CreateDWordField (^RBUF, ^COM4._BAS, BAS4) - CreateDWordField (^RBUF, ^COM4._LEN, LEN3) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) Store (^^PCRB (PID_GPIOCOM4), BAS4) - Store (GPIO_BASE_SIZE, LEN3) + Store (GPIO_BASE_SIZE, LEN4) Return (RBUF) } @@ -69,19 +84,31 @@ Device (GPIO) Method (GADD, 1, NotSerialized) { /* GPIO Community 0 */ - If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_G7))) + If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPIO_RSVD_11))) { Store (PID_GPIOCOM0, Local0) Subtract (Arg0, GPP_A0, Local1) } /* GPIO Community 1 */ - If (LAnd (LGreaterEqual (Arg0, GPP_D0), LLessEqual (Arg0, GPP_H23))) + If (LAnd (LGreaterEqual (Arg0, GPP_D0), LLessEqual (Arg0, GPIO_RSVD_52))) { Store (PID_GPIOCOM1, Local0) Subtract (Arg0, GPP_D0, Local1) } + /* GPIO Community 2 */ + If (LAnd (LGreaterEqual (Arg0, GPD0), LLessEqual (Arg0, GPD11))) + { + Store (PID_GPIOCOM1, Local0) + Subtract (Arg0, GPD0, Local1) + } + /* GPIO Community 3 */ + If (LAnd (LGreaterEqual (Arg0, HDA_BCLK), LLessEqual (Arg0, GPIO_RSVD_78))) + { + Store (PID_GPIOCOM1, Local0) + Subtract (Arg0, HDA_BCLK, Local1) + } /* GPIO Community 04*/ - If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_E23))) + If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPIO_RSVD_67))) { Store (PID_GPIOCOM4, Local0) Subtract (Arg0, GPP_C0, Local1) |