Unify setting 82801a/b/c/d IOAPIC ID

Remove obscure local copy of writing the ioapic registers.

Change-Id: I133e710639ff57c6a0ac925e30efce2ebc43b856
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/2532
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

8 files changed, 87 insertions, 86 deletions

diff --git a/src/southbridge/intel/i82801ax/Kconfig b/src/southbridge/intel/i82801ax/Kconfig
index 70734a7a15..71ae0163c2 100644
--- a/src/southbridge/intel/i82801ax/Kconfig
+++ b/src/southbridge/intel/i82801ax/Kconfig
@@ -19,6 +19,7 @@
 
 config SOUTHBRIDGE_INTEL_I82801AX
 	bool
+	select IOAPIC
 	select HAVE_HARD_RESET
 	select USE_WATCHDOG_ON_BOOT
 
diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c
index c9404ed3c0..1d296f414d 100644
--- a/src/southbridge/intel/i82801ax/lpc.c
+++ b/src/southbridge/intel/i82801ax/lpc.c
@@ -70,17 +70,30 @@ typedef struct southbridge_intel_i82801ax_config config_t;
  * Use the defined IRQ values above or set mainboard
  * specific IRQ values in your devicetree.cb.
  */
-static void i82801ax_enable_apic(struct device *dev)
-{
-	u32 reg32;
-	volatile u32 *ioapic_index = (volatile u32 *)IO_APIC_ADDR;
-	volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
 
+
+/**
+ * Enable ACPI I/O range.
+ *
+ * @param dev PCI device with ACPI and PM BAR's
+ */
+static void i82801ax_enable_acpi(struct device *dev)
+{
 	/* Set ACPI base address (I/O space). */
 	pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
 
 	/* Enable ACPI I/O range decode and ACPI power management. */
 	pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
+}
+
+/**
+ * Set miscellanous static southbridge features.
+ *
+ * @param dev PCI device with I/O APIC control registers
+ */
+static void i82801ax_enable_ioapic(struct device *dev)
+{
+	u32 reg32;
 
 	reg32 = pci_read_config32(dev, GEN_CNTL);
 	reg32 |= (1 << 13);	/* Coprocessor error enable (COPR_ERR_EN) */
@@ -90,18 +103,7 @@ static void i82801ax_enable_apic(struct device *dev)
 	pci_write_config32(dev, GEN_CNTL, reg32);
 	printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
 
-	*ioapic_index = 0;
-	*ioapic_data = (1 << 25);
-
-	*ioapic_index = 0;
-	reg32 = *ioapic_data;
-	printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32);
-	if (reg32 != (1 << 25))
-		die("APIC Error\n");
-
-	/* TODO: From i82801ca, needed/useful on other ICH? */
-	*ioapic_index = 3; /* Select Boot Configuration register. */
-	*ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
+	set_ioapic_id(IO_APIC_ADDR, 0x02);
 }
 
 static void i82801ax_enable_serial_irqs(struct device *dev)
@@ -219,8 +221,9 @@ static void lpc_init(struct device *dev)
 	/* Set the value for PCI command register. */
 	pci_write_config16(dev, PCI_COMMAND, 0x000f);
 
+	i82801ax_enable_acpi(dev);
 	/* IO APIC initialization. */
-	i82801ax_enable_apic(dev);
+	i82801ax_enable_ioapic(dev);
 
 	i82801ax_enable_serial_irqs(dev);
 
diff --git a/src/southbridge/intel/i82801bx/Kconfig b/src/southbridge/intel/i82801bx/Kconfig
index 00cb5bfa90..3d725d473c 100644
--- a/src/southbridge/intel/i82801bx/Kconfig
+++ b/src/southbridge/intel/i82801bx/Kconfig
@@ -19,6 +19,7 @@
 
 config SOUTHBRIDGE_INTEL_I82801BX
 	bool
+	select IOAPIC
 	select HAVE_HARD_RESET
 	select USE_WATCHDOG_ON_BOOT
 
diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c
index 0ff44e6054..0533afbdae 100644
--- a/src/southbridge/intel/i82801bx/lpc.c
+++ b/src/southbridge/intel/i82801bx/lpc.c
@@ -72,17 +72,29 @@ typedef struct southbridge_intel_i82801bx_config config_t;
  * Use the defined IRQ values above or set mainboard
  * specific IRQ values in your devicetree.cb.
 */
-static void i82801bx_enable_apic(struct device *dev)
-{
-	uint32_t reg32;
-	volatile uint32_t *ioapic_index = (volatile uint32_t *)IO_APIC_ADDR;
-	volatile uint32_t *ioapic_data = (volatile uint32_t *)(IO_APIC_ADDR + 0x10);
 
+/**
+ * Enable ACPI I/O range.
+ *
+ * @param dev PCI device with ACPI and PM BAR's
+ */
+static void i82801bx_enable_acpi(struct device *dev)
+{
 	/* Set ACPI base address (I/O space). */
 	pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
 
 	/* Enable ACPI I/O range decode and ACPI power management. */
 	pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
+}
+
+/**
+ * Set miscellanous static southbridge features.
+ *
+ * @param dev PCI device with I/O APIC control registers
+ */
+static void i82801bx_enable_ioapic(struct device *dev)
+{
+	u32 reg32;
 
 	reg32 = pci_read_config32(dev, GEN_CNTL);
 	reg32 |= (1 << 13);	/* Coprocessor error enable (COPR_ERR_EN) */
@@ -92,18 +104,7 @@ static void i82801bx_enable_apic(struct device *dev)
 	pci_write_config32(dev, GEN_CNTL, reg32);
 	printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
 
-	*ioapic_index = 0;
-	*ioapic_data = (1 << 25);
-
-	*ioapic_index = 0;
-	reg32 = *ioapic_data;
-	printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32);
-	if (reg32 != (1 << 25))
-		die("APIC Error\n");
-
-	/* TODO: From i82801ca, needed/useful on other ICH? */
-	*ioapic_index = 3; /* Select Boot Configuration register. */
-	*ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
+	set_ioapic_id(IO_APIC_ADDR, 0x02);
 }
 
 static void i82801bx_enable_serial_irqs(struct device *dev)
@@ -237,8 +238,10 @@ static void lpc_init(struct device *dev)
 	/* Set the value for PCI command register. */
 	pci_write_config16(dev, PCI_COMMAND, 0x000f);
 
+	i82801bx_enable_acpi(dev);
+
 	/* IO APIC initialization. */
-	i82801bx_enable_apic(dev);
+	i82801bx_enable_ioapic(dev);
 
 	i82801bx_enable_serial_irqs(dev);
 
diff --git a/src/southbridge/intel/i82801cx/Kconfig b/src/southbridge/intel/i82801cx/Kconfig
index 17e90e83a3..3e01cb81c7 100644
--- a/src/southbridge/intel/i82801cx/Kconfig
+++ b/src/southbridge/intel/i82801cx/Kconfig
@@ -1,4 +1,4 @@
 config SOUTHBRIDGE_INTEL_I82801CX
 	bool
+	select IOAPIC
 	select HAVE_HARD_RESET
-
diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c
index a1ffb8f540..79998bc722 100644
--- a/src/southbridge/intel/i82801cx/lpc.c
+++ b/src/southbridge/intel/i82801cx/lpc.c
@@ -24,34 +24,24 @@
 #define MAINBOARD_POWER_ON  1
 
 
-static void i82801cx_enable_ioapic( struct device *dev)
+/**
+ * Set miscellanous static southbridge features.
+ *
+ * @param dev PCI device with I/O APIC control registers
+ */
+static void i82801cx_enable_ioapic(struct device *dev)
 {
-	uint32_t dword;
-    volatile uint32_t* ioapic_index = (volatile uint32_t*)IO_APIC_ADDR;
-    volatile uint32_t* ioapic_data = (volatile uint32_t*)(IO_APIC_ADDR + 0x10);
-
-    dword = pci_read_config32(dev, GEN_CNTL);
-    dword |= (3 << 7); /* enable ioapic & disable SMBus interrupts */
-    dword |= (1 <<13); /* coprocessor error enable */
-    dword |= (1 << 1); /* delay transaction enable */
-    dword |= (1 << 2); /* DMA collection buf enable */
-    pci_write_config32(dev, GEN_CNTL, dword);
-    printk(BIOS_DEBUG, "ioapic southbridge enabled %x\n",dword);
-
-    // Must program the APIC's ID before using it
-
-    *ioapic_index = 0;		// Select APIC ID register
-    *ioapic_data = (2<<24);
-
-    // Hang if the ID didn't take (chip not present?)
-    *ioapic_index = 0;
-    dword = *ioapic_data;
-    printk(BIOS_DEBUG, "Southbridge apic id = %x\n", (dword>>24) & 0xF);
-    if(dword != (2<<24))
-		die("");
-
-	*ioapic_index = 3;		// Select Boot Configuration register
-	*ioapic_data = 1;		// Use Processor System Bus to deliver interrupts
+	u32 reg32;
+
+	reg32 = pci_read_config32(dev, GEN_CNTL);
+	reg32 |= (1 << 13);	/* Coprocessor error enable (COPR_ERR_EN) */
+	reg32 |= (3 << 7);	/* IOAPIC enable (APIC_EN) */
+	reg32 |= (1 << 2);	/* DMA collection buffer enable (DCB_EN) */
+	reg32 |= (1 << 1);	/* Delayed transaction enable (DTE) */
+	pci_write_config32(dev, GEN_CNTL, reg32);
+	printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
+
+	set_ioapic_id(IO_APIC_ADDR, 0x02);
 }
 
 // This is how interrupts are received from the Super I/O chip
diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h
index d9e4d3809d..2da77591f5 100644
--- a/src/southbridge/intel/i82801dx/i82801dx.h
+++ b/src/southbridge/intel/i82801dx/i82801dx.h
@@ -82,6 +82,7 @@ int smbus_read_byte(unsigned device, unsigned address);
 #define   PMBASE_ADDR	0x0400
 #define   DEFAULT_PMBASE PMBASE_ADDR
 #define ACPI_CNTL       0x44
+#define   ACPI_EN	(1 << 4)
 #define BIOS_CNTL       0x4E
 #define GPIO_BASE       0x58
 #define GPIO_CNTL       0x5C
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c
index fbf8e12228..0644569c71 100644
--- a/src/southbridge/intel/i82801dx/lpc.c
+++ b/src/southbridge/intel/i82801dx/lpc.c
@@ -36,37 +36,38 @@
 
 typedef struct southbridge_intel_i82801dx_config config_t;
 
-static void i82801dx_enable_ioapic(struct device *dev)
+/**
+ * Enable ACPI I/O range.
+ *
+ * @param dev PCI device with ACPI and PM BAR's
+ */
+static void i82801dx_enable_acpi(struct device *dev)
 {
-	u32 reg32;
-	volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
-	volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
-
 	/* Set ACPI base address (I/O space). */
 	pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
 
-	/* Enable ACPI I/O and power management. */
-	pci_write_config8(dev, ACPI_CNTL, 0x10);
+	/* Enable ACPI I/O range decode and ACPI power management. */
+	pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
+}
+
+/**
+ * Set miscellanous static southbridge features.
+ *
+ * @param dev PCI device with I/O APIC control registers
+ */
+static void i82801dx_enable_ioapic(struct device *dev)
+{
+	u32 reg32;
 
 	reg32 = pci_read_config32(dev, GEN_CNTL);
-	reg32 |= (3 << 7);	/* Enable IOAPIC */
-	reg32 |= (1 << 13);	/* Coprocessor error enable */
-	reg32 |= (1 << 1);	/* Delayed transaction enable */
-	reg32 |= (1 << 2);	/* DMA collection buffer enable */
+	reg32 |= (1 << 13);	/* Coprocessor error enable (COPR_ERR_EN) */
+	reg32 |= (3 << 7);	/* IOAPIC enable (APIC_EN) */
+	reg32 |= (1 << 2);	/* DMA collection buffer enable (DCB_EN) */
+	reg32 |= (1 << 1);	/* Delayed transaction enable (DTE) */
 	pci_write_config32(dev, GEN_CNTL, reg32);
 	printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
 
-	*ioapic_index = 0;
-	*ioapic_data = (1 << 25);
-
-	*ioapic_index = 0;
-	reg32 = *ioapic_data;
-	printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32);
-	if (reg32 != (1 << 25))
-		die("APIC Error\n");
-
-	*ioapic_index = 3; /* Select Boot Configuration register. */
-	*ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
+	set_ioapic_id(IO_APIC_ADDR, 0x02);
 }
 
 static void i82801dx_enable_serial_irqs(struct device *dev)
@@ -267,6 +268,7 @@ static void lpc_init(struct device *dev)
 	/* Set the value for PCI command register. */
 	pci_write_config16(dev, PCI_COMMAND, 0x000f);
 
+	i82801dx_enable_acpi(dev);
 	/* IO APIC initialization. */
 	i82801dx_enable_ioapic(dev);