I am so stupid to mix up logical and bitwise NOT.

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2191 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 51 insertions, 59 deletions

diff --git a/src/mainboard/amd/rumba/auto.c b/src/mainboard/amd/rumba/auto.c
index 160fddc72f..9163374cff 100644
--- a/src/mainboard/amd/rumba/auto.c
+++ b/src/mainboard/amd/rumba/auto.c
@@ -15,26 +15,36 @@
 #include "cpu/x86/msr.h"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+static void dump_msr(void)
+{
+	int i = 0;
+	msr_t msr;
+
+	static const unsigned int msrs[] = { 0x20000018, 0x20000019, 0x0};
+
+	while (msrs[i] != 0) {
+		msr = rdmsr(msrs[i]);
+		print_debug("MSR ");
+		print_debug_hex32(msrs[i]);
+		print_debug("=> ");
+		print_debug_hex32(msr.hi);
+		print_debug(":");
+		print_debug_hex32(msr.lo);
+		print_debug("\n\r");
+		i++;
+	}
+}
 
 //#include "lib/delay.c"
 #include "northbridge/amd/gx2/raminit.h"
 #include "northbridge/amd/gx2/raminit.c"
 #include "sdram/generic_sdram.c"
 
+
 static void msr_init(void)
 {
 
 	__builtin_wrmsr(0x1808,  0x10f3bf00, 0x22fffc02);
-/* Ollie: here are some registers I think you should also set. */
-#if 0
-	/* FIX THIS FOR RUMBA -- this is LIPPERT SETTING */
-	__builtin_wrmsr(0x10000018, 0, 0x10076013);
-	__builtin_wrmsr(0x10000019, 0x696332a3, 0x18000008);
-	__builtin_wrmsr(0x1000001a, 0x101, 0);
-	__builtin_wrmsr(0x1000001c, 0xff00ff, 0);
-	__builtin_wrmsr(0x1000001d, 0x300, 0);
-	__builtin_wrmsr(0x1000001f, 0, 0);
-#endif	
 	__builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
         __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
         __builtin_wrmsr(0x10000026, 0x400fffc0, 0x2cfbc040);
@@ -79,7 +89,7 @@ static void pll_reset(void)
 	msr.hi = 0x00000019;
 	msr.lo = 0x06de0378;
 	wrmsr(0x4c000014, msr);
-	msr.lo |= ((0xde << 16) | (1 << 26));
+	msr.lo |= ((0xde << 16) | (1 << 26) | (1 << 24));
 	wrmsr(0x4c000014, msr);
 
 	print_debug("Reset PLL\n\r");
@@ -98,40 +108,23 @@ static void main(unsigned long bist)
 	};
 
 	msr_init();
-
+	
 	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 	uart_init();
 	console_init();
 
-	print_err("hi\n\r");
-
 	pll_reset();
+
 	msr_init();
 
+
 	/* Halt if there was a built in self test failure */
 	//report_bist_failure(bist);
 	
 	sdram_initialize(1, memctrl);
+
 	
 	/* Check all of memory */
-	ram_check(0x00000000, 1024*1024);
-
-#if 0
-	ram_check(0x00000000, msr.lo);
-
-	static const struct {
-		unsigned long lo, hi;
-	} check_addrs[] = {
-		/* Check 16MB of memory @ 0*/
-		{ 0x00000000, 0x01000000 },
-#if TOTAL_CPUS > 1
-		/* Check 16MB of memory @ 2GB */
-		{ 0x80000000, 0x81000000 },
-#endif
-	};
-	int i;
-	for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
-		ram_check(check_addrs[i].lo, check_addrs[i].hi);
-	}
-#endif
+	ram_check(0x00000000, 640*1024);
+
 }
diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c
index ebe558e885..e0b5d0e75e 100644
--- a/src/northbridge/amd/gx2/raminit.c
+++ b/src/northbridge/amd/gx2/raminit.c
@@ -21,60 +21,62 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	print_debug("sdram_enable step 1\r\n");
 	msr = rdmsr(0x20000018);
 	msr.hi = 0x10076013;
-	msr.lo = 0x00004800;
+	msr.lo = 0x00003000;
 	wrmsr(0x20000018, msr);
 
 	msr = rdmsr(0x20000019);
 	msr.hi = 0x18000108;
-	msr.lo = 0x286332a3;
+	msr.lo = 0x696332a3;
 	wrmsr(0x20000019, msr);
 
-	/* 2. release from PMode */
+	/* 2. clock gating for PMode */
 	msr = rdmsr(0x20002004);
-	msr.lo &= !0x04;
-	msr.lo |= 0x03;
+	msr.lo &= ~0x04;
+	msr.lo |=  0x01;
 	wrmsr(0x20002004, msr);
 	/* undocmented bits in GX, in LX there are
 	 * 8 bits in PM1_UP_DLY */
 	msr = rdmsr(0x2000001a);
-	//msr.lo |= 0xF000;
 	msr.lo = 0x0101;
 	wrmsr(0x2000001a, msr);
 	print_debug("sdram_enable step 2\r\n");
 
 	/* 3. release CKE mask to enable CKE */
 	msr = rdmsr(0x2000001d);
-	msr.lo &= !(0x03 << 8);
+	msr.lo &= ~(0x03 << 8);
 	wrmsr(0x2000201d, msr);
 	print_debug("sdram_enable step 3\r\n");
 
-	/* 4. set and clear REF_TST 16 times, more shouldn't hurt */
+	/* 4. set and clear REF_TST 16 times, more shouldn't hurt
+	 * why this is before EMRS and MRS ? */
 	for (i = 0; i < 19; i++) {
 		msr = rdmsr(0x20000018);
 		msr.lo |=  (0x01 << 3);
 		wrmsr(0x20000018, msr);
-		msr.lo &= !(0x01 << 3);
+		msr.lo &= ~(0x01 << 3);
 		wrmsr(0x20000018, msr);
 	}
 	print_debug("sdram_enable step 4\r\n");
 
 	/* 5. set refresh interval */
 	msr = rdmsr(0x20000018);
-	msr.lo |= (0x48 << 8);
+	msr.lo &= ~(0xffff << 8);
+	msr.lo |=  (0x34 << 8);
 	wrmsr(0x20000018, msr);
-
 	/* set refresh staggering to 4 SDRAM clocks */
 	msr = rdmsr(0x20000018);
-	msr.lo &= !(0x03 << 6);
+	msr.lo &= ~(0x03 << 6);
+	msr.lo |=  (0x00 << 6);
 	wrmsr(0x20000018, msr);
+	print_debug("sdram_enable step 5\r\n");
 
-	/* 6. enable RLL, load Extended Mode Register by set and clear PROG_DRAM */
+	/* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */
 	msr = rdmsr(0x20000018);
 	msr.lo |=  ((0x01 << 28) | 0x01);
 	wrmsr(0x20000018, msr);
-	msr.lo &= !((0x01 << 28) | 0x01);
+	msr.lo &= ~((0x01 << 28) | 0x01);
 	wrmsr(0x20000018, msr);
-	print_debug("sdram_enable step 7\r\n");
+	print_debug("sdram_enable step 6\r\n");
 
 	/* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
 	 * it is documented in LX datasheet  */	
@@ -82,19 +84,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	msr = rdmsr(0x20000018);
 	msr.lo |=  ((0x01 << 27) | 0x01);
 	wrmsr(0x20000018, msr);
-	msr.lo &= !((0x01 << 27) | 0x01);
+	msr.lo &= ~((0x01 << 27) | 0x01);
 	wrmsr(0x20000018, msr);
-	print_debug("sdram_enable step 9\r\n");
-
+	print_debug("sdram_enable step 7\r\n");
 
 	/* 8. load Mode Register by set and clear PROG_DRAM */
 	msr = rdmsr(0x20000018);
 	msr.lo |=  0x01;
 	wrmsr(0x20000018, msr);
-	msr.lo &= !0x01;
+	msr.lo &= ~0x01;
 	wrmsr(0x20000018, msr);
-	print_debug("sdram_enable step 10\r\n");
-
+	print_debug("sdram_enable step 8\r\n");
 
 	/* wait 200 SDCLKs */
 	for (i = 0; i < 200; i++)
@@ -102,15 +102,14 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 	/* load RDSYNC */
 	msr = rdmsr(0x2000001f);
-	msr.hi = 0x000ff310;
+	msr.hi = 0x000ff300;
 	msr.lo = 0x00000000;
 	wrmsr(0x2000001f, msr);
-	print_debug("sdram_enable step 10\r\n");
 
 	/* set delay control */
 	msr = rdmsr(0x4c00000f);
-	msr.hi = 0x830d415f;
-	msr.lo = 0x8ea0ad6f;
+	msr.hi = 0x830d415a;
+	msr.lo = 0x8ea0ad6a;
 	wrmsr(0x4c00000f, msr);
 
 	/* DRAM working now?? */