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authorSubrata Banik <subrata.banik@intel.com>2019-03-25 21:49:39 +0530
committerSubrata Banik <subrata.banik@intel.com>2019-03-27 04:39:48 +0000
commited6996f2babb6efd794e45e18f39a09d2996b2b0 (patch)
treeee5b96b7cf4560ff3d307fdddaccb2466c4b2061 /src
parente651e01518d904bf661db90fb986af82db04a843 (diff)
downloadcoreboot-ed6996f2babb6efd794e45e18f39a09d2996b2b0.tar.xz
device/pciexp_device: Convert LTR non-snoop/snoop value into common macro
Change-Id: I3d14a40b4ed0dcc216dcac883e33749b7808f00d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src')
-rw-r--r--src/include/device/pciexp.h5
-rw-r--r--src/soc/intel/broadwell/pcie.c4
-rw-r--r--src/soc/intel/common/block/pcie/pcie.c8
3 files changed, 10 insertions, 7 deletions
diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h
index 0f1420a013..3a9825d871 100644
--- a/src/include/device/pciexp.h
+++ b/src/include/device/pciexp.h
@@ -14,6 +14,11 @@ enum aspm_type {
#define ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET 29
#define ASPM_LTR_L12_THRESHOLD_SCALE_MASK (0x7 << ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET)
+/* Latency tolerance reporting, max non-snoop latency value 3.14ms */
+#define PCIE_LTR_MAX_NO_SNOOP_LATENCY_3146US 0x1003
+/* Latency tolerance reporting, max snoop latency value 3.14ms */
+#define PCIE_LTR_MAX_SNOOP_LATENCY_3146US 0x1003
+
void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,
unsigned int max_devfn);
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index 472e8da465..dff4f8139f 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -652,7 +652,9 @@ static void pch_pcie_enable(struct device *dev)
static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off)
{
/* Set max snoop and non-snoop latency for Broadwell */
- pci_write_config32(dev, off, 0x10031003);
+ pci_write_config32(dev, off,
+ PCIE_LTR_MAX_NO_SNOOP_LATENCY_3146US << 16 |
+ PCIE_LTR_MAX_SNOOP_LATENCY_3146US);
}
static struct pci_operations pcie_ops = {
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index d74b09826c..e8b1050f4a 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -21,10 +21,6 @@
#include <device/pci_ops.h>
#define CACHE_LINE_SIZE 0x10
-/* Latency tolerance reporting, max non-snoop latency value 3.14ms */
-#define PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE 0x1003
-/* Latency tolerance reporting, max snoop latency value 3.14ms */
-#define PCIE_LTR_MAX_SNOOP_LATENCY_VALUE 0x1003
static void pch_pcie_init(struct device *dev)
{
@@ -66,8 +62,8 @@ static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset)
{
/* Set max snoop and non-snoop latency for the SOC */
pci_write_config32(dev, offset,
- PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE << 16 |
- PCIE_LTR_MAX_SNOOP_LATENCY_VALUE);
+ PCIE_LTR_MAX_NO_SNOOP_LATENCY_3146US << 16 |
+ PCIE_LTR_MAX_SNOOP_LATENCY_3146US);
}
static struct pci_operations pcie_ops = {