diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-25 15:26:58 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-29 07:18:55 +0000 |
commit | f0a017fe8288e16adbecf8998e99c2cadc3e12de (patch) | |
tree | dd058a40a224d25ef0836aa28db2ad1bb188cca2 /src | |
parent | 9895177517a796093ef11616bff8a35b0437610f (diff) | |
download | coreboot-f0a017fe8288e16adbecf8998e99c2cadc3e12de.tar.xz |
sb/intel/bd828x6x: Make CONFIG_ELOG=y compile
The function pch_log_state() was overlooked when making the smi
relocation code common.
Change-Id: I878772f1a93105b828e50f37e105d04988ba0bdf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src')
-rw-r--r-- | src/southbridge/intel/bd82x6x/elog.c | 1 | ||||
-rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 3 | ||||
-rw-r--r-- | src/southbridge/intel/common/pmutil.h | 1 | ||||
-rw-r--r-- | src/southbridge/intel/common/smi.c | 6 |
4 files changed, 5 insertions, 6 deletions
diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c index 3299d4b9d1..2ccdf83c4d 100644 --- a/src/southbridge/intel/bd82x6x/elog.c +++ b/src/southbridge/intel/bd82x6x/elog.c @@ -21,6 +21,7 @@ #include <stdint.h> #include <string.h> #include <elog.h> +#include <southbridge/intel/common/pmutil.h> #include "pch.h" void pch_log_state(void) diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 280ac7d6ef..ff55c393d7 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -66,9 +66,6 @@ int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -#if IS_ENABLED(CONFIG_ELOG) -void pch_log_state(void); -#endif #else /* __PRE_RAM__ */ void enable_smbus(void); void enable_usb_bar(void); diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 47813f7d02..2076a3d2c1 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -149,5 +149,6 @@ void southbridge_update_gnvs(u8 apm_cnt, int *smm_done); void southbridge_finalize_all(void); void southbridge_smi_monitor(void); em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd); +void pch_log_state(void); #endif /*INTEL_COMMON_PMUTIL_H */ diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 3ce4f4057a..af9dd5d87d 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -23,6 +23,7 @@ #include <cpu/x86/smm.h> #include <cpu/intel/smm/gen1/smi.h> #include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/common/pmutil.h> #include "pmutil.h" @@ -39,10 +40,9 @@ void southbridge_smm_init(void) u16 pm1_en; u32 gpe0_en; -#if IS_ENABLED(CONFIG_ELOG) + if (IS_ENABLED(CONFIG_ELOG)) /* Log events from chipset before clearing */ - pch_log_state(); -#endif + pch_log_state(); printk(BIOS_DEBUG, "Initializing southbridge SMI..."); |