soc/intel/common/block/cpu: Add option to skip coreboot AP init

SoC users from IOTG team is looking forward for a solution to skip
coreboot AP initialization flow and make use of FSPS-UPD to
perform AP reset.

TEST=Assign use_fsp_mp_init=1 to ensure coreboot is not bringing APs
out of reset.

Change-Id: Ibc8cd411e802fb682436a933073922b2693ba994
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

11 files changed, 49 insertions, 26 deletions

diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index 71fed875de..e541bfe5af 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -143,7 +143,9 @@ chip soc/intel/skylake
 	}"
 
 	# Skip coreboot MP Init
-	register "use_fsp_mp_init" = "1"
+	register "common_soc_config" = "{
+		.use_fsp_mp_init = 1,
+	}"
 
 	# Enable x1 slot
 	register "PcieRpEnable[7]" = "1"
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 31b6b1747f..081bba373e 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -28,9 +28,10 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <intelblocks/acpi.h>
+#include <intelblocks/chip.h>
 #include <intelblocks/fast_spi.h>
-#include <intelblocks/p2sb.h>
 #include <intelblocks/msr.h>
+#include <intelblocks/p2sb.h>
 #include <intelblocks/xdci.h>
 #include <fsp/api.h>
 #include <fsp/util.h>
@@ -614,7 +615,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
 	if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK))
 		silconfig->MonitorMwaitEnable = 0;
 
-	silconfig->SkipMpInit = !cfg->use_fsp_mp_init;
+	silconfig->SkipMpInit = !chip_get_fsp_mp_init();
 
 	/* Disable setting of EISS bit in FSP. */
 	silconfig->SpiEiss = 0;
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 4f586acfd1..61ddedaf49 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -150,13 +150,6 @@ struct soc_intel_apollolake_config {
 	 * (1) Power
 	 * (2) Power & Performance */
 	enum pnp_settings pnp_settings;
-
-	/*
-	 * Option for mainboard to skip coreboot MP initialization
-	 * 0 = Make use of coreboot MP Init
-	 * 1 = Make use of FSP MP Init
-	 */
-	uint8_t use_fsp_mp_init;
 };
 
 typedef struct soc_intel_apollolake_config config_t;
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 924764a6c8..30719ed5b1 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -21,6 +21,7 @@
 #include <fsp/api.h>
 #include <fsp/util.h>
 #include <intelblocks/acpi.h>
+#include <intelblocks/chip.h>
 #include <intelblocks/xdci.h>
 #include <romstage_handoff.h>
 #include <soc/intel/common/vbt.h>
@@ -295,7 +296,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 
 	params->Heci3Enabled = config->Heci3Enabled;
 	params->Device4Enable = config->Device4Enable;
-	params->SkipMpInit = !config->use_fsp_mp_init;
+	params->SkipMpInit = !chip_get_fsp_mp_init();
 
 	/* VrConfig Settings for 5 domains
 	 * 0 = System Agent, 1 = IA Core, 2 = Ring,
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index a269659f12..4704d1cef6 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -201,12 +201,6 @@ struct soc_intel_cannonlake_config {
 	uint8_t TcoIrqSelect;
 	uint8_t TcoIrqEnable;
 
-	/*
-	 * Option for mainboard to skip coreboot MP initialization
-	 * 0 = Make use of coreboot MP Init
-	 * 1 = Make use of FSP MP Init
-	 */
-	uint8_t use_fsp_mp_init;
 	/* VrConfig Settings for 5 domains
 	 * 0 = System Agent, 1 = IA Core, 2 = Ring,
 	 * 3 = GT unsliced,  4 = GT sliced */
diff --git a/src/soc/intel/common/block/chip/chip.c b/src/soc/intel/common/block/chip/chip.c
index cfec4eca39..aecf060e3f 100644
--- a/src/soc/intel/common/block/chip/chip.c
+++ b/src/soc/intel/common/block/chip/chip.c
@@ -32,3 +32,18 @@ const struct soc_intel_common_config *chip_get_common_soc_structure(void)
 
 	return soc_config;
 }
+
+/*
+ * This function will get MP Init config
+ *
+ * Return values:
+ * 0 = Make use of coreboot MP Init
+ * 1 = Make use of FSP MP Init
+ */
+int chip_get_fsp_mp_init(void)
+{
+	const struct soc_intel_common_config *common_config;
+	common_config = chip_get_common_soc_structure();
+
+	return common_config->use_fsp_mp_init;
+}
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index e264348055..fd0ac992b5 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -22,6 +22,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mp.h>
 #include <cpu/intel/microcode.h>
+#include <intelblocks/chip.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/mp_init.h>
@@ -124,6 +125,9 @@ static void init_cpus(void *unused)
 	struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER);
 	assert(dev != NULL);
 
+	if (chip_get_fsp_mp_init())
+		return;
+
 	microcode_patch = intel_microcode_find();
 	intel_microcode_load_unlocked(microcode_patch);
 
@@ -138,6 +142,9 @@ static void wrapper_x86_setup_mtrrs(void *unused)
 /* Ensure to re-program all MTRRs based on DRAM resource settings */
 static void post_cpus_init(void *unused)
 {
+	if (chip_get_fsp_mp_init())
+		return;
+
 	if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL, 1000) < 0)
 		printk(BIOS_ERR, "MTRR programming failure\n");
 
diff --git a/src/soc/intel/common/block/include/intelblocks/chip.h b/src/soc/intel/common/block/include/intelblocks/chip.h
index 555bdaa893..d761f6be76 100644
--- a/src/soc/intel/common/block/include/intelblocks/chip.h
+++ b/src/soc/intel/common/block/include/intelblocks/chip.h
@@ -33,9 +33,24 @@ struct soc_intel_common_config {
 	int chipset_lockdown;
 	struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
 	struct dw_i2c_bus_config i2c[CONFIG_SOC_INTEL_I2C_DEV_MAX];
+	/*
+	 * Option for mainboard to skip coreboot MP initialization
+	 * 0 = Make use of coreboot MP Init
+	 * 1 = Make use of FSP MP Init
+	 */
+	uint8_t use_fsp_mp_init;
 };
 
 /* This function to retrieve soc config structure required by common code */
 const struct soc_intel_common_config *chip_get_common_soc_structure(void);
 
+/*
+ * This function will get MP Init config
+ *
+ * Return values:
+ * 0 = Make use of coreboot MP Init
+ * 1 = Make use of FSP MP Init
+ */
+int chip_get_fsp_mp_init(void);
+
 #endif /* SOC_INTEL_COMMON_BLOCK_CHIP_H */
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index e8023ba0ce..6927831100 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -20,6 +20,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <fsp/util.h>
+#include <intelblocks/chip.h>
 #include <intelblocks/xdci.h>
 #include <intelpch/lockdown.h>
 #include <soc/acpi.h>
@@ -172,7 +173,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 	params->SerialIrqConfigStartFramePulse =
 		config->SerialIrqConfigStartFramePulse;
 
-	params->SkipMpInit = !config->use_fsp_mp_init;
+	params->SkipMpInit = !chip_get_fsp_mp_init();
 
 	for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++)
 		params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 3c85ad5a3d..9f78e5c3b8 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -434,13 +434,6 @@ struct soc_intel_skylake_config {
 	} SerialIrqConfigStartFramePulse;
 
 	/*
-	 * Option for mainboard to skip coreboot MP initialization
-	 * 0 = Make use of coreboot MP Init
-	 * 1 = Make use of FSP MP Init
-	 */
-	u8 use_fsp_mp_init;
-
-	/*
 	 * VrConfig Settings for 5 domains
 	 * 0 = System Agent, 1 = IA Core, 2 = Ring,
 	 * 3 = GT unsliced,  4 = GT sliced
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 00c7163a2f..a2bd16bd53 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -29,6 +29,7 @@
 #include <device/pci_ids.h>
 #include <fsp/api.h>
 #include <fsp/util.h>
+#include <intelblocks/chip.h>
 #include <intelblocks/xdci.h>
 #include <intelpch/lockdown.h>
 #include <romstage_handoff.h>
@@ -388,7 +389,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	params->PchSirqEnable = config->SerialIrqConfigSirqEnable;
 	params->PchSirqMode = config->SerialIrqConfigSirqMode;
 
-	params->CpuConfig.Bits.SkipMpInit = !config->use_fsp_mp_init;
+	params->CpuConfig.Bits.SkipMpInit = !chip_get_fsp_mp_init();
 
 	for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++)
 		params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];